JP2001083943A - Liquid crystal display device and drive method - Google Patents

Liquid crystal display device and drive method

Info

Publication number
JP2001083943A
JP2001083943A JP25522899A JP25522899A JP2001083943A JP 2001083943 A JP2001083943 A JP 2001083943A JP 25522899 A JP25522899 A JP 25522899A JP 25522899 A JP25522899 A JP 25522899A JP 2001083943 A JP2001083943 A JP 2001083943A
Authority
JP
Japan
Prior art keywords
common electrode
driving circuit
liquid crystal
line driving
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25522899A
Other languages
Japanese (ja)
Other versions
JP3402277B2 (en
Inventor
Katsumi Adachi
克己 足達
Makoto Yamakura
誠 山倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25522899A priority Critical patent/JP3402277B2/en
Publication of JP2001083943A publication Critical patent/JP2001083943A/en
Application granted granted Critical
Publication of JP3402277B2 publication Critical patent/JP3402277B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PROBLEM TO BE SOLVED: To simplify the structure of an output circuit and make the potential of one value variable so that a bright regulation can be realized by synchronizing a common electrode line driving circuit with a scanning line drive circuit, and setting the output binary. SOLUTION: The output of a common electrode line drive circuit 112 is binary, and it is arranged on the same side as a scanning line drive circuit 110. A scanning line waveform Vg and a signal line waveform Vs are changed in IH time unit and repeated in IV period. This is repeated, whereby an amplitude larger than the signal waveform Vs can be obtained. Since the common line electrode potential is binary, the positive side and the negative side have the same amplitude, and the common electrode Vc of a liquid crystal 107 is set lower than the center value of the signal line waveform Vs by the portion of the slight shift to the negative side according to the Voff change of a scanning line waveform Vg, whereby the application of DC to the liquid crystal 107 can be prevented, and a problem such as flicker or seizure is never caused. Accordingly, the common electrode line drive circuit 112 can reconcile the increase in picture element electrode potential Vd and the suppression of the scanning line waveform Vg.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はアクティブマトリク
ス方式の液晶表示装置及び駆動方法に関し、信号側駆動
回路の振幅低減と走査側駆動回路の振幅低減を同時に行
い、かつ実用性を高めたものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and a driving method, which simultaneously reduce the amplitude of a signal side driving circuit and the amplitude of a scanning side driving circuit, and improve the practicality. .

【0002】[0002]

【従来の技術】アクティブマトリクス方式の液晶表示装
置において、液晶の保持特性を高めるための保持容量を
前段走査線と画素間に作り、ここから液晶にバイアス電
圧を印可する対向一定容量結合駆動方法と呼ばれる方法
がある(例えば日経BP社 フラットパネル・ディスプ
レイ’93 P128〜P131)。これは信号側最大
振幅の抑制(5Vで十分)と内部直流電圧の抑制等をね
らったものである。これに対し、この方法の欠点である
走査側振幅の増大を防ぐために、補助容量を前段ゲート
間でなく、独立な補助電極接続とし、この補助電極にパ
ルス状波形を加えて液晶にバイアス電位を加えるという
方法が提案されている(特開平10−39277)。図
8にその構成を、図5にその動作波形を示し、図と共に
説明する。
2. Description of the Related Art In an active matrix type liquid crystal display device, a fixed capacitance coupling driving method for forming a storage capacitor between a preceding scanning line and a pixel and applying a bias voltage to the liquid crystal from the former is provided. There is a method called (for example, Nikkei BP Flat Panel Display '93 P128-P131). This aims at suppressing the maximum amplitude on the signal side (5 V is sufficient), suppressing the internal DC voltage, and the like. On the other hand, in order to prevent an increase in the amplitude on the scanning side, which is a drawback of this method, the auxiliary capacitance is not connected between the preceding gates but is connected to an independent auxiliary electrode. There has been proposed a method of adding (JP-A-10-39277). FIG. 8 shows its configuration, and FIG. 5 shows its operation waveforms.

【0003】図8において、画像表示部内には複数の信
号線101と、それと直交する複数の走査線102、そ
れらの交点近傍に設けられたスイッチング素子103
と、これに接続された画素電極104と、走査線102
と対になり概平行配置された共通電極線105と、画素
電極104に一端を接続し他端は共通電極線105に接
続された保持容量106と、液晶107を介して対向す
るコモン電極Vcが配置されている。
[0003] In FIG. 8, a plurality of signal lines 101, a plurality of scanning lines 102 orthogonal to the signal lines 101, and a switching element 103 provided near an intersection thereof are provided in an image display unit.
And the pixel electrode 104 connected thereto and the scanning line 102
A common electrode line 105 which is paired with the common electrode line 105, a storage capacitor 106 having one end connected to the pixel electrode 104 and the other end connected to the common electrode line 105, and a common electrode Vc opposed via a liquid crystal 107. Are located.

【0004】スイッチング素子は一般的には非晶質シリ
コン(a−Si)、最近では多結晶ポリシリコン(p−
Si)、反射投射型パネル等に用途を絞ればICに用い
られる単結晶シリコン(c−Si)で形成される。それ
らはデバイスの構造上ゲート−ドレイン間容量108が
あり、これにより走査線102からのゲートパルスが画
素電極104を負側にシフトする現象が発生する。
The switching element is generally made of amorphous silicon (a-Si), and recently, polycrystalline polysilicon (p-Si).
If the application is limited to a reflective projection type panel or the like, it is formed of single crystal silicon (c-Si) used for an IC. They have a gate-drain capacitance 108 due to the structure of the device, which causes a phenomenon that a gate pulse from the scanning line 102 shifts the pixel electrode 104 to the negative side.

【0005】画素表示部以外では信号線101を駆動す
るための信号線駆動回路109、走査線102を駆動す
る走査線駆動回路110、共通電極線105を駆動する
ための共通電極線駆動回路111が周辺に配置される。
走査駆動回路110はスタート信号V−Sとクロック信
号Vclkを基に出力はVoffとVonの2値を発生
するシフトレジスタとバッファから構成される。同様に
共通電極線駆動回路111はスタート信号V−Sとクロ
ック信号Vclkを基に出力はVe−とVeとVe+の
3値を発生するシフトレジスタとスイッチから構成され
る。
In areas other than the pixel display portion, a signal line driving circuit 109 for driving the signal lines 101, a scanning line driving circuit 110 for driving the scanning lines 102, and a common electrode line driving circuit 111 for driving the common electrode lines 105 are provided. It is arranged around.
The scan driving circuit 110 is composed of a shift register and a buffer for generating binary values of Voff and Von based on the start signal VS and the clock signal Vclk. Similarly, the common electrode line driving circuit 111 is composed of a shift register and a switch that generate three values of Ve−, Ve and Ve + based on the start signal VS and the clock signal Vclk.

【0006】次に動作を図5の波形図とともに説明す
る。ある走査線の波形VgはH期間幅でVonであり、
次のフィルード期間(=V期間)はVoffに保持し、
後にVonをH期間出力し、これを繰り返す。信号線駆
動回路109は映像信号によって異なるが、一様な信号
が入力されているとすると図5に示すようにH期間毎に
極性の反転した信号Vsが出力される。画素電極104
の電位VdはVgがVonの期間、スイッチング素子1
03は導通し信号線波形Vs(この場合負極性)と同電
位となる。この期間内に共通電極線105の電位をVe
からVe+にしておく。そしてVgがVoffとなる瞬
間、ゲート−ドレイン間容量108を通じて画素電極電
位は僅かに負にシフトする(ゲート−ドレイン間容量1
08は液晶107の容量と保持容量106の総和よりも
一桁小さい)。その後、共通電極線105の電位がVe
+からVeに下がるため、画素電極電位Vdはほぼこの
電位差分負側にシフトし、次のVgがVonになるまで
スイッチング素子が遮断状態であるので保持される。次
のVonの期間、Vsは正極性であり、Vdは負側から
正側のVsまで充電される。この期間共通電極105の
電位をVeからVe−にしておく。そして同様にVon
からVoffの瞬間、僅かな負側シフトした後、共通電
極105の電位がVe−からVeに上がり、Vdは正側
にこの電位差分シフトし、保持される。
Next, the operation will be described with reference to the waveform diagram of FIG. The waveform Vg of a certain scanning line is Von with an H period width,
The next field period (= V period) is held at Voff,
Later, Von is output for the H period, and this is repeated. The signal line driving circuit 109 differs depending on the video signal, but assuming that a uniform signal is input, a signal Vs whose polarity is inverted every H period is output as shown in FIG. Pixel electrode 104
Of the switching element 1 during the period when Vg is Von.
03 conducts and has the same potential as the signal line waveform Vs (in this case, negative polarity). During this period, the potential of the common electrode line 105 is set to Ve.
To Ve +. At the moment when Vg becomes Voff, the pixel electrode potential shifts slightly negatively through the gate-drain capacitance 108 (gate-drain capacitance 1).
08 is one digit smaller than the sum of the capacity of the liquid crystal 107 and the storage capacity 106). After that, the potential of the common electrode line 105 becomes Ve.
Since the voltage drops from + to Ve, the pixel electrode potential Vd substantially shifts to the negative side of the potential difference, and is held until the next Vg becomes Von because the switching element is in the cutoff state. During the next Von, Vs is positive and Vd is charged from the negative side to the positive side Vs. During this period, the potential of the common electrode 105 is changed from Ve to Ve−. And similarly Von
After a slight negative shift at the moment from Voff to Voff, the potential of the common electrode 105 rises from Ve− to Ve, and Vd shifts by this potential difference to the positive side and is held.

【0007】これを繰り返して信号線Vsの振幅よりも
大きな振幅を画素電極に与えることが可能となる。この
時、Ve+とVe−の振幅を効率よくVdに伝達するた
めには保持容量を大きくして液晶容量との比を数倍にし
ておく方が望ましい。以上述べた動作により、走査線波
形VgはVonからVoffまでの振幅に抑えられる効
果を得るものである。
By repeating this, it becomes possible to give an amplitude larger than the amplitude of the signal line Vs to the pixel electrode. At this time, in order to efficiently transmit the amplitudes of Ve + and Ve- to Vd, it is desirable to increase the storage capacitance and increase the ratio to the liquid crystal capacitance several times. By the operation described above, the scanning line waveform Vg has an effect of being suppressed to the amplitude from Von to Voff.

【0008】[0008]

【発明が解決しようとする課題】しかし、従来の構成と
方法では、まず共通電極の出力値が3値であるので、共
通電極駆動回路の構成が単純なバッファ構成ではでき
ず、煩雑になる。そしてこの共通電極の出力を形成する
さいに液晶パネルのブライト調整のためVe+とVe−
の振幅を連動して調整する必要があり、通常は低出力イ
ンピーダンスのオペアンプを複数個用いるため、実装面
積や消費電力の増大が問題となった。さらに走査線駆動
回路と共通電極駆動回路を両側に構成すると回路の信号
線や電源を引きまわせばならなくなり、パネルの周辺サ
イズの増大や外部回路との接続個所が複数になるおそれ
がある。また、保持容量を大きくするとパネルの開口率
が低下し暗くなるという課題もあった。
However, in the conventional configuration and method, since the output value of the common electrode is three-valued first, the configuration of the common electrode driving circuit cannot be made with a simple buffer configuration, and becomes complicated. When forming the output of the common electrode, Ve + and Ve- are used to adjust the brightness of the liquid crystal panel.
It is necessary to adjust the amplitude in conjunction with each other. Usually, since a plurality of operational amplifiers having low output impedance are used, the mounting area and the power consumption increase. Furthermore, if the scanning line driving circuit and the common electrode driving circuit are formed on both sides, the signal lines and the power supply of the circuit must be drawn, which may increase the peripheral size of the panel and increase the number of connection points with external circuits. In addition, there is another problem that when the storage capacity is increased, the aperture ratio of the panel is reduced and the panel becomes dark.

【0009】[0009]

【課題を解決するための手段】本願の第1の発明は、第
1の基板上に設けられた複数の信号線と、これを駆動す
る信号線駆動回路と、前記信号線と直交する複数の走査
線と、これを駆動する走査線駆動回路と、前記信号線と
前記走査線の交点近傍に設けられたスイッチング素子
と、前記スイッチング素子に接続された画素電極と、前
記走査線と対になり概平行配置された共通電極線と、前
記画素電極に一端を接続し他端は前記共通電極線に接続
された保持容量と、前記共通電極を駆動する共通電極駆
動回路と、前記第1の基板と液晶層を介して対峙するコ
モン電極を持つ第2の基板とからなり、前記共通電極駆
動回路は前記走査線駆動回路と同期しかつ出力を2値と
するものである。
According to a first aspect of the present invention, a plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the plurality of signal lines, and a plurality of signal lines orthogonal to the signal lines are provided. A scanning line, a scanning line driving circuit for driving the scanning line, a switching element provided near an intersection of the signal line and the scanning line, a pixel electrode connected to the switching element, and a pair with the scanning line. A common electrode line arranged substantially in parallel, a storage capacitor having one end connected to the pixel electrode and the other end connected to the common electrode line, a common electrode driving circuit for driving the common electrode, and the first substrate And a second substrate having a common electrode facing each other via a liquid crystal layer. The common electrode driving circuit synchronizes with the scanning line driving circuit and outputs a binary value.

【0010】本願の第2の発明は、第1の基板上に設け
られた複数の信号線と、これを駆動する信号線駆動回路
と、前記信号線と直交する複数の走査線と、これを駆動
する走査線駆動回路と、前記信号線と前記走査線の交点
近傍に設けられたスイッチング素子と、前記スイッチン
グ素子に接続された画素電極と、前記走査線と対になり
概平行配置された共通電極線と、前記画素電極に一端を
接続し他端は前記共通電極線に接続された保持容量と、
前記共通電極を駆動する共通電極駆動回路と、前記第1
の基板と液晶層を介して対峙するコモン電極を持つ第2
の基板とからなり、前記走査線駆動回路と前記共通電極
駆動回路は表示画面に対して片側にまとめて配置し、入
力信号を一部共用するものである。
According to a second aspect of the present invention, a plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the plurality of signal lines, a plurality of scanning lines orthogonal to the signal lines, and A scanning line driving circuit to be driven; a switching element provided near an intersection of the signal line and the scanning line; a pixel electrode connected to the switching element; An electrode line, a storage capacitor having one end connected to the pixel electrode and the other end connected to the common electrode line,
A common electrode driving circuit for driving the common electrode;
Having a common electrode opposed to the substrate through a liquid crystal layer
The scanning line driving circuit and the common electrode driving circuit are arranged on one side of a display screen and share an input signal.

【0011】本願の第3の発明は、第1の基板上に設け
られた複数の信号線と、これを駆動する信号線駆動回路
と、前記信号線と直交する複数の走査線と、これを駆動
する走査線駆動回路と、前記信号線と前記走査線の交点
近傍に設けられたスイッチング素子と、前記スイッチン
グ素子に接続された画素電極と、前記走査線と対になり
概平行配置された共通電極線と、前記画素電極に一端を
接続し他端は前記共通電極線に接続された保持容量と、
前記共通電極を駆動する共通電極駆動回路と、前記第1
の基板と液晶層を介して対峙するコモン電極を持つ第2
の基板とからなり、前記画素電極が反射型電極とするも
のである。
According to a third aspect of the present invention, a plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the plurality of signal lines, a plurality of scanning lines orthogonal to the signal lines, and A scanning line driving circuit to be driven; a switching element provided near an intersection of the signal line and the scanning line; a pixel electrode connected to the switching element; An electrode line, a storage capacitor having one end connected to the pixel electrode and the other end connected to the common electrode line,
A common electrode driving circuit for driving the common electrode;
Having a common electrode opposed to the substrate through a liquid crystal layer
And the pixel electrode is a reflective electrode.

【0012】[0012]

【発明の実施の形態】本発明の第1の実施例を図1に示
し、図と共に説明する。基本的に図8と同一機能のもの
は同一番号を付す。信号線駆動回路109と走査線駆動
回路110並びに画素表示部は図8と同等の動作を行っ
ている。共通電極線駆動回路112は図8と異なり、出
力は2値であり、さらに走査線駆動回路110と同一側
に配置される。図2に波形を示し、動作を説明する。走
査線波形Vgと信号線波形Vsは図5と同等に1H期間
単位で変化し、1V期間周期を繰り返している。最初の
Vonの期間に画素電極電位Vdは負極性の信号線波形
Vsと同電位となり、その後のVgがVoffへの変化
時の僅かな負のシフトが発生する。ここまでは図5と同
様である。その期間の共通線電極電位はVe+を前のフ
ィールド期間から保っており、このVgがVoffにな
った後、Ve+からVe−に下がり、この振幅分Vdを
負側にシフトさせる。そしてフィルード期間(=V期
間)この状態を保持し、次のVon期間にVdをVsの
正極側に充電する。その次のVdの僅かな負シフトの
後、共通線電極電位をVe−からVe+へと上げ、この
振幅分Vdを正側にシフトさせる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIG. Basically, components having the same functions as those in FIG. The signal line driving circuit 109, the scanning line driving circuit 110, and the pixel display section perform operations equivalent to those in FIG. The common electrode line driving circuit 112 is different from FIG. 8 in that the output is binary, and is further arranged on the same side as the scanning line driving circuit 110. FIG. 2 shows waveforms, and the operation will be described. The scanning line waveform Vg and the signal line waveform Vs change in 1H period units as in FIG. 5, and repeat the 1V period cycle. During the first Von period, the pixel electrode potential Vd becomes the same potential as the negative signal line waveform Vs, and a slight negative shift occurs when Vg subsequently changes to Voff. Up to this point, it is the same as FIG. During this period, the common line electrode potential keeps Ve + from the previous field period, and after this Vg becomes Voff, it falls from Ve + to Ve-, and this amplitude Vd is shifted to the negative side. Then, this state is maintained during the field period (= V period), and Vd is charged to the positive side of Vs in the next Von period. After the next slight negative shift of Vd, the common line electrode potential is raised from Ve− to Ve +, and the amplitude Vd is shifted to the positive side by this amplitude.

【0013】これを繰り返して図5同様に信号線波形V
sよりも大きな振幅を得ることが可能となる。この場
合、共通線電極電位は2値なので、正側と負側も同一振
幅となり、VgのVoff変化に伴う僅かな負側シフト
の分、液晶107のコモン電極Vcを信号線波形Vsの
センタ値より下げておけば液晶にDCが印可されること
なくフリッカ、焼き付き等の問題は発生しない。これに
より、共通電極線駆動回路112は2値の出力であって
も、Vdの増大とVgの抑制を両立することが可能とな
る。
By repeating this, the signal line waveform V
It is possible to obtain an amplitude larger than s. In this case, since the common line electrode potential has two values, the positive side and the negative side have the same amplitude, and the common electrode Vc of the liquid crystal 107 is shifted to the center value of the signal line waveform Vs by a slight negative side shift accompanying the Voff change of Vg. If the temperature is lowered further, no DC is applied to the liquid crystal, and no problems such as flicker and burn-in occur. As a result, even when the common electrode line drive circuit 112 has a binary output, it is possible to achieve both an increase in Vd and a suppression of Vg.

【0014】そして、図1に示すように走査線駆動回路
110と共通電極線駆動回路112は同一側に配置され
るため、スタート信号V−Sとクロック信号Vclkを
共通に使用できる。図示はしてないが他に電源配線等も
共通化が可能となり、配線引き回しが短くなる、外部回
路の接続も基本的に一個所ですむという利点が得られ
る。
Since the scanning line driving circuit 110 and the common electrode line driving circuit 112 are arranged on the same side as shown in FIG. 1, the start signal VS and the clock signal Vclk can be used in common. Although not shown, power supply wiring and the like can be shared in addition to the above, so that there are advantages that wiring can be shortened, and connection of an external circuit is basically required at one place.

【0015】次に本発明の別な観点を述べる。図2で説
明したように、ある走査線と共通電極線のペアにとり、
フィールド期間で1回の共通電極線の変化があり、この
ペアが垂直方向にシフトしながら、全画面の書き込みを
行う。つまり、共通電極線駆動回路112にとり、変化
するのは1H期間に1本の共通電極線であり、それ以外
の共通電極線は保持状態にある。発明者らはこれに注目
し共通線電極駆動回路112の出力インピーダンスの許
容値を求めてみると、パネルサイズによって異なるがほ
ぼ数kΩのオーダーであることが判明した。このことと
2値出力であるということからブライト調整を1個の可
変抵抗器で行うことが可能となる。液晶印加電圧の大小
を調整して画像の明るさを変える、いわゆるブライト調
整は、従来図5に示す共通電極線の振幅、Ve+とVe
−の振幅を変えることで行っていた。このVe+とVe
−の振幅を連動して変えるということはオペアンプを2
個以上使う複雑な構成をとらざるをえなかった。
Next, another aspect of the present invention will be described. As described in FIG. 2, for a pair of a certain scanning line and a common electrode line,
There is one change of the common electrode line during the field period, and the writing of the entire screen is performed while this pair shifts in the vertical direction. That is, for the common electrode line driving circuit 112, only one common electrode line changes during the 1H period, and the other common electrode lines are in a holding state. The inventors paid attention to this and found the allowable value of the output impedance of the common line electrode drive circuit 112, and found that the allowable value was on the order of several kΩ, depending on the panel size. Because of this and the binary output, the brightness adjustment can be performed by one variable resistor. The so-called bright adjustment in which the brightness of the image is changed by adjusting the magnitude of the liquid crystal applied voltage is conventionally performed by using the amplitudes of common electrode lines, Ve + and Ve + shown in FIG.
This was done by changing the amplitude of-. This Ve + and Ve
Changing the-amplitude in conjunction means that the operational amplifier
I had to take a complicated configuration that uses more than one.

【0016】本発明ではこれが図3に示す簡単な構成で
可能である。図3において201は可変抵抗器であり、
既存の回路の電源Vddと接地電位Vssの間に接続
し、中点をVe+として共通線電極駆動回路112の出
力回路に接続してある。通常のツイストネマティック液
晶ではVssが5V程度、Ve+とVe−の振幅が4V
から5Vで正常な画面が得られるので、Vddとしては
ありふれた+5V電源が使用可能である。もし、ブライ
ト調整が不要ないし信号線駆動回路109にその機能が
あるならば、Ve−とVe+は固定電源に接続してもか
まわないのは当然である。
In the present invention, this is possible with the simple configuration shown in FIG. In FIG. 3, reference numeral 201 denotes a variable resistor;
It is connected between the power supply Vdd and the ground potential Vss of the existing circuit, and the middle point is connected to the output circuit of the common line electrode drive circuit 112 as Ve +. In a normal twisted nematic liquid crystal, Vss is about 5V, and the amplitude of Ve + and Ve- is 4V.
Since a normal screen can be obtained from 5 V, a common +5 V power supply can be used as Vdd. If the brightness adjustment is unnecessary or the signal line driving circuit 109 has the function, it is natural that Ve- and Ve + may be connected to a fixed power supply.

【0017】なお、図3ではVssを共通して使用して
いるがその逆にVddを共通とし、Ve−側を可変して
も良く、その効果は変わらない。そしてある瞬間では1
本の共通電極線のみ変化し、それ以外の共通電極線は保
持状態にある点を更に検討すると他の共通電極線自身が
平滑コンデンサとして動作し、別途図3の可変抵抗器2
01の中点に別途平滑コンデンサを付加する必要が実用
上ないことを見出した。これにより構成が更に簡便とな
った。これらの利点は信号線駆動回路109がディジタ
ル入力の構成時に全体的なブライト調整がしにくいため
特に大きいものがある。
Although Vss is commonly used in FIG. 3, Vdd may be commonly used and Ve- side may be varied, and the effect is not changed. And at one moment 1
Considering further that only one of the common electrode lines changes and the other common electrode lines are in a holding state, the other common electrode lines themselves operate as smoothing capacitors, and the variable resistor 2 shown in FIG.
It has been found that it is practically unnecessary to add a separate smoothing capacitor to the midpoint of 01. This has further simplified the configuration. These advantages are particularly significant when the signal line driving circuit 109 has a digital input configuration, so that it is difficult to perform overall brightness adjustment.

【0018】この出力インピーダンスと平滑コンデンサ
不要の観点は従来の3値出力の共通電極線駆動回路11
1でも適用できる。その全体構成を図4に示す。図1と
同機能のものは同一番号を付し説明を省略する。図1と
異なるのは共通電極線駆動回路113が3値、Ve−と
VeとVe+という点である。この具体例を図6に示
す。図6の可変抵抗器202と可変抵抗器203にてV
e+とVe−を作り出す。平滑コンデンサ不要な点も前
述同様である。
This output impedance and the fact that a smoothing capacitor is not required are based on the conventional ternary output common electrode line driving circuit 11.
Even 1 can be applied. FIG. 4 shows the overall configuration. Components having the same functions as those in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted. The difference from FIG. 1 is that the common electrode line drive circuit 113 has three values, Ve−, Ve and Ve +. This specific example is shown in FIG. V is applied to the variable resistor 202 and the variable resistor 203 in FIG.
Create e + and Ve-. The point where a smoothing capacitor is unnecessary is the same as the above.

【0019】本発明の別な実施例を図7に示し図と共に
説明する。図7は反射型液晶に適用した場合の1画素の
平面図を示したもので、101は信号線、102は走査
線、103はスイッチング素子、104は画素電極、1
05は共通電極線、斜線部106は保持容量である。こ
こで画素電極104は通常アルミニウムの反射板構成で
最上部に形成される。これに対し一般的な透過型液晶の
画素電極はITO等の透明導体で構成され、共通電極線
105を太くするとこの共通電極線は金属のため遮光さ
れて暗くなるという欠点があった。反射型液晶構成で
は、保持容量106の面積も表示に有効に使用できる。
つまり、保持容量を大きくして共通電極線駆動回路の振
幅を小さくすることに対して開口率の低下という不利の
ない構成とすることができる。
Another embodiment of the present invention is shown in FIG. 7 and will be described with reference to the drawings. FIG. 7 is a plan view of one pixel when applied to a reflection type liquid crystal, wherein 101 is a signal line, 102 is a scanning line, 103 is a switching element, 104 is a pixel electrode,
Reference numeral 05 denotes a common electrode line, and a hatched portion 106 denotes a storage capacitor. Here, the pixel electrode 104 is usually formed on the uppermost portion with a reflecting plate structure of aluminum. On the other hand, a pixel electrode of a general transmissive liquid crystal is made of a transparent conductor such as ITO, and when the common electrode line 105 is made thicker, the common electrode line is shielded from light by a metal and becomes dark. In the reflective liquid crystal configuration, the area of the storage capacitor 106 can be effectively used for display.
In other words, it is possible to achieve a configuration that is not disadvantageous in that the aperture ratio is reduced when the storage capacitor is increased and the amplitude of the common electrode line driving circuit is reduced.

【0020】本発明は走査線と共通電極線というペアで
駆動するため、通常の走査線数よりも2倍の駆動回路が
必要となる。このため、これらの駆動回路を外付けする
よりも、多結晶シリコンや単結晶シリコンにより画素表
示部のスイッチング素子と同一基板に内蔵する構成の方
が接続点数も少なくすみ実用性が高い。むろん動作速度
は10kHz〜30kHzであるので非晶質シリコでも
動作可能である。
Since the present invention is driven by a pair of a scanning line and a common electrode line, a driving circuit having twice the number of ordinary scanning lines is required. For this reason, a configuration in which the switching elements of the pixel display unit are built in the same substrate with polycrystalline silicon or single crystal silicon has a smaller number of connection points and is more practical than a case where these driving circuits are externally provided. Of course, since the operation speed is 10 kHz to 30 kHz, it is possible to operate even with amorphous silicon.

【0021】[0021]

【発明の効果】本発明の第1の実施例によれば共通電極
線駆動回路の出力が2値ですむので、その出力回路の構
成が簡単になり、このうち片方の電位を可変とすること
でブライト調整を実現できる。
According to the first embodiment of the present invention, the output of the common electrode line drive circuit is binary, so that the configuration of the output circuit is simplified, and one of the potentials is made variable. The brightness adjustment can be realized with.

【0022】本発明の第2の実施例によれば走査線駆動
回路と共通線駆動回路を片側に隣接して配置することに
より、接続線や電源線の共通化が図れ、周辺回路部の面
積縮小と外部回路への接続個所を1つにすることが可能
となる。
According to the second embodiment of the present invention, by arranging the scanning line driving circuit and the common line driving circuit adjacent to one side, connection lines and power supply lines can be shared, and the area of the peripheral circuit portion can be increased. It is possible to reduce the number of connections and the number of connections to external circuits to one.

【0023】本発明の第3の実施例によれば、画素電極
を反射型構成とするため、保持容量を大きくして共通電
極線駆動回路の振幅を小さくすることに対して開口率の
低下という不利のない構成とすることができる。
According to the third embodiment of the present invention, since the pixel electrodes are of the reflection type, the aperture ratio is reduced as compared with reducing the amplitude of the common electrode line drive circuit by increasing the storage capacitance. A configuration without disadvantage can be obtained.

【0024】別な観点からは、可変抵抗器に簡便な構成
でブライト調整が可能となる利点がある。さらに走査線
駆動回路や共通電極線駆動回路を画面表示部のスイッチ
ング素子と同一基板上に同一工程で形成する内蔵回路と
することでより実用性は高まる。
From another viewpoint, there is an advantage that the brightness can be adjusted with a simple configuration of the variable resistor. Further, by forming the scanning line driving circuit and the common electrode line driving circuit on the same substrate as the switching elements of the screen display portion on the same substrate in the same process, the practicality is further enhanced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の本発明の構成図FIG. 1 is a configuration diagram of a first present invention.

【図2】第1の本発明の動作説明図FIG. 2 is an explanatory diagram of the operation of the first present invention.

【図3】電圧発生の構成図FIG. 3 is a configuration diagram of voltage generation.

【図4】第2の本発明の構成図FIG. 4 is a block diagram of the second invention.

【図5】第2の本発明の動作説明図FIG. 5 is a diagram for explaining the operation of the second invention.

【図6】第2の本発明の電圧発生の構成図FIG. 6 is a configuration diagram of the voltage generation according to the second invention.

【図7】第3の本発明による画素構成図FIG. 7 is a pixel configuration diagram according to the third invention.

【図8】従来の構成図FIG. 8 is a conventional configuration diagram.

【符号の説明】[Explanation of symbols]

101 信号線 102 走査線 103 スイッチング素子 104 画素電極 105 共通電極線 106 保持容量 107 液晶 108 ゲート−ドレイン間容量 109 信号線駆動回路 110 走査線駆動回路 111,112,113 共通電極線駆動回路 201,202,203 可変抵抗器 Reference Signs List 101 signal line 102 scanning line 103 switching element 104 pixel electrode 105 common electrode line 106 storage capacitance 107 liquid crystal 108 gate-drain capacitance 109 signal line driving circuit 110 scanning line driving circuit 111, 112, 113 common electrode line driving circuit 201, 202 , 203 Variable resistor

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 2H093 NA16 NB13 NC03 NC09 NC18 NC21 NC34 NC35 ND07 ND10 ND38 5C006 AF44 AF52 BB16 BC03 BC12 BC20 BF25 BF37 FA43 FA47 FA54 5C080 AA10 BB05 DD03 EE28 FF11 JJ02 JJ03 JJ04  ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H093 NA16 NB13 NC03 NC09 NC18 NC21 NC34 NC35 ND07 ND10 ND38 5C006 AF44 AF52 BB16 BC03 BC12 BC20 BF25 BF37 FA43 FA47 FA54 5C080 AA10 BB05 DD03 EE28 FF11 JJ02 JJ03 JJ04

Claims (27)

【特許請求の範囲】[Claims] 【請求項1】第1の基板上に設けられた複数の信号線
と、前記信号線を駆動する信号線駆動回路と、前記信号
線と直交する複数の走査線と、前記走査線を駆動する走
査線駆動回路と、前記信号線と前記走査線の交点近傍に
設けられたスイッチング素子と、前記スイッチング素子
に接続された画素電極と、前記走査線と対になり概平行
配置された共通電極線と、前記画素電極に一端を接続し
他端は前記共通電極線に接続された保持容量と、前記共
通電極線を駆動する共通電極線駆動回路と、前記第1の
基板と液晶層を介して対峙するコモン電極を持つ第2の
基板とからなり、前記共通電極線駆動回路は前記走査線
駆動回路と同期しかつ出力が2値であることを特徴とす
る液晶表示装置。
1. A plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the signal lines, a plurality of scanning lines orthogonal to the signal lines, and driving the scanning lines A scanning line driving circuit, a switching element provided near an intersection of the signal line and the scanning line, a pixel electrode connected to the switching element, and a common electrode line paired with the scanning line and arranged substantially in parallel with the scanning line A storage capacitor connected to the pixel electrode at one end and the other end connected to the common electrode line, a common electrode line driving circuit for driving the common electrode line, and the first substrate and the liquid crystal layer. A liquid crystal display device comprising a second substrate having common electrodes facing each other, wherein the common electrode line driving circuit is synchronized with the scanning line driving circuit and has a binary output.
【請求項2】前記共通電極線駆動回路の2値の出力うち
片方が可変であることを特徴とする請求項1記載の液晶
表示装置。
2. The liquid crystal display device according to claim 1, wherein one of binary outputs of said common electrode line drive circuit is variable.
【請求項3】前記信号線駆動回路がディジタル信号入力
であることを特徴とする請求項2記載の液晶表示装置。
3. The liquid crystal display device according to claim 2, wherein said signal line drive circuit is a digital signal input.
【請求項4】前記共通電極線駆動回路の出力のうち、片
方ないし両方が抵抗を介して固定電源に接続されたこと
を特徴とする請求項1記載の液晶表示装置。
4. The liquid crystal display device according to claim 1, wherein one or both of the outputs of the common electrode line drive circuit are connected to a fixed power supply via a resistor.
【請求項5】前記共通電極線駆動回路の出力には平滑コ
ンデンサが接続されていないことを特徴とする請求項1
記載の液晶表示装置。
5. A smoothing capacitor is not connected to an output of said common electrode line driving circuit.
The liquid crystal display device as described in the above.
【請求項6】前記走査線駆動回路と前記共通電極線駆動
回路が多結晶シリコンを用い、かつ第1の基板上に形成
されていることを特徴とする請求項1記載の液晶表示装
置。
6. The liquid crystal display device according to claim 1, wherein said scanning line driving circuit and said common electrode line driving circuit are made of polycrystalline silicon and formed on a first substrate.
【請求項7】前記走査線駆動回路と前記共通電極線駆動
回路が非晶質シリコンを用い、かつ第1の基板上に形成
されていることを特徴とする請求項1記載の液晶表示装
置。
7. The liquid crystal display device according to claim 1, wherein said scanning line driving circuit and said common electrode line driving circuit are made of amorphous silicon and formed on a first substrate.
【請求項8】前記走査線駆動回路と前記共通電極線駆動
回路が単結晶シリコンを用い、かつ第1の基板上に形成
されていることを特徴とする請求項1記載の液晶表示装
置。
8. The liquid crystal display device according to claim 1, wherein said scanning line driving circuit and said common electrode line driving circuit are formed of single crystal silicon and formed on a first substrate.
【請求項9】第1の基板上に設けられた複数の信号線
と、前記信号線を駆動する信号線駆動回路と、前記信号
線と直交する複数の走査線と、前記走査線を駆動する走
査線駆動回路と、前記信号線と前記走査線の交点近傍に
設けられたスイッチング素子と、前記スイッチング素子
に接続された画素電極と、前記走査線と対になり概平行
配置された共通電極線と、前記画素電極に一端を接続し
他端は前記共通電極線に接続された保持容量と、前記共
通電極線を駆動する共通電極線駆動回路と、前記第1の
基板と液晶層を介して対峙する第2の基板とからなり、
前記共通電極は対となる走査電極がオンからオフに変化
後、ある電位Aからもう一つの電位Bに変化することで
補助容量を通じて画素電極に一定のバイアス電圧を与
え、共通電極の電位Bは1フィールド期間を保持し、つ
ぎの走査電極がオンからオフに変化した後に共通電極を
電位Aに戻すことで画素電極に逆のバイアス電圧を与
え、フリッカ調整はDCであるコモン電極電位を調整す
ることを特徴とする液晶表示装置の駆動方法。
9. A plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the signal lines, a plurality of scanning lines orthogonal to the signal lines, and driving the scanning lines. A scanning line driving circuit, a switching element provided near an intersection of the signal line and the scanning line, a pixel electrode connected to the switching element, and a common electrode line paired with the scanning line and arranged substantially in parallel with the scanning line A storage capacitor connected to the pixel electrode at one end and the other end connected to the common electrode line, a common electrode line driving circuit for driving the common electrode line, and the first substrate and the liquid crystal layer. Consisting of a second substrate facing
The common electrode applies a constant bias voltage to the pixel electrode through an auxiliary capacitor by changing from a certain potential A to another potential B after a pair of scanning electrodes change from on to off, and the common electrode potential B is By maintaining one field period and returning the common electrode to the potential A after the next scanning electrode changes from on to off, a reverse bias voltage is applied to the pixel electrode, and flicker adjustment adjusts the DC common electrode potential. A method for driving a liquid crystal display device, comprising:
【請求項10】前記共通電極の電位Aないし電位Bのう
ちどちらかを可変とし、ブライト調整機能を持たせるこ
とを特徴とする請求項9記載の液晶表示装置の駆動方
法。
10. A driving method for a liquid crystal display device according to claim 9, wherein one of the potentials A and B of said common electrode is made variable to have a brightness adjusting function.
【請求項11】第1の基板上に設けられた複数の信号線
と、前記信号線を駆動する信号線駆動回路と、前記信号
線と直交する複数の走査線と、前記走査線を駆動する走
査線駆動回路と、前記信号線と前記走査線の交点近傍に
設けられたスイッチング素子と、前記スイッチング素子
に接続された画素電極と、前記走査線と対になり概平行
配置された共通電極線と、前記画素電極に一端を接続し
他端は前記共通電極線に接続された保持容量と、前記共
通電極を駆動する共通電極駆動回路と、前記第1の基板
と液晶層を介して対峙するコモン電極を持つ第2の基板
とからなり、前記共通電極駆動回路は前記走査線駆動回
路と同期しかつ出力が画素電極に正のバイアス電圧を与
えるa値のパルスと画素電極に負のバイアス電位を与え
るb値のパルスからなり、大部分の期間は一定のc値で
ある3値からなり、a値とb値は固定電源から抵抗を通
じて与えられることを特徴とする液晶表示装置。
11. A plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the signal lines, a plurality of scanning lines orthogonal to the signal lines, and driving the scanning lines. A scanning line driving circuit, a switching element provided near an intersection of the signal line and the scanning line, a pixel electrode connected to the switching element, and a common electrode line paired with the scanning line and arranged substantially in parallel with the scanning line A storage capacitor connected to the pixel electrode at one end and the other end connected to the common electrode line, a common electrode driving circuit for driving the common electrode, and the first substrate facing the first substrate via a liquid crystal layer. A second substrate having a common electrode, wherein the common electrode driving circuit synchronizes with the scanning line driving circuit and outputs a pulse having an a value giving a positive bias voltage to the pixel electrode and a negative bias potential applied to the pixel electrode. B pulse giving Becomes, the liquid crystal display device where most of the period consists of three values is a constant value c, a value and b value, characterized in that provided through the resistor from a fixed power source.
【請求項12】前記共通電極線駆動回路の出力には平滑
コンデンサが接続されていないことを特徴とする請求項
11記載の液晶表示装置。
12. The liquid crystal display device according to claim 11, wherein a smoothing capacitor is not connected to an output of said common electrode line driving circuit.
【請求項13】第1の基板上に設けられた複数の信号線
と、前記信号線を駆動する信号線駆動回路と、前記信号
線と直交する複数の走査線と、前記走査線を駆動する走
査線駆動回路と、前記信号線と前記走査線の交点近傍に
設けられたスイッチング素子と、前記スイッチング素子
に接続された画素電極と、前記走査線と対になり概平行
配置された共通電極線と、前記画素電極に一端を接続し
他端は前記共通電極線に接続された保持容量と、前記共
通電極線を駆動する共通電極線駆動回路と、前記第1の
基板と液晶層を介して対峙するコモン電極を持つ第2の
基板とからなり、前記走査線駆動回路と前記共通電極線
駆動回路は表示画面に対して片側にまとめて配置され、
入力信号を一部共用することを特徴とする液晶表示装
置。
13. A plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the signal lines, a plurality of scanning lines orthogonal to the signal lines, and driving the scanning lines. A scanning line driving circuit, a switching element provided near an intersection of the signal line and the scanning line, a pixel electrode connected to the switching element, and a common electrode line paired with the scanning line and arranged substantially in parallel with the scanning line A storage capacitor connected to the pixel electrode at one end and the other end connected to the common electrode line, a common electrode line driving circuit for driving the common electrode line, and the first substrate and the liquid crystal layer. The scanning line driving circuit and the common electrode line driving circuit are collectively arranged on one side with respect to a display screen;
A liquid crystal display device characterized by partially sharing an input signal.
【請求項14】前記走査線駆動回路と前記共通電極線駆
動回路が多結晶シリコンを用い、かつ第1の基板上に形
成されていることを特徴とする請求項13記載の液晶表
示装置。
14. The liquid crystal display device according to claim 13, wherein said scanning line driving circuit and said common electrode line driving circuit are formed of polycrystalline silicon and formed on a first substrate.
【請求項15】前記走査線駆動回路と前記共通電極線駆
動回路が非晶質シリコンを用い、かつ第1の基板上に形
成されていることを特徴とする請求項13記載の液晶表
示装置。
15. The liquid crystal display device according to claim 13, wherein said scanning line driving circuit and said common electrode line driving circuit use amorphous silicon and are formed on a first substrate.
【請求項16】前記走査線駆動回路と前記共通電極線駆
動回路が単結晶シリコンを用い、かつ第1の基板上に形
成されていることを特徴とする請求項13記載の液晶表
示装置。
16. The liquid crystal display device according to claim 13, wherein said scanning line driving circuit and said common electrode line driving circuit are formed of single crystal silicon and formed on a first substrate.
【請求項17】第1の基板上に設けられた複数の信号線
と、前記信号線を駆動する信号線駆動回路と、前記信号
線と直交する複数の走査線と、前記走査線を駆動する走
査線駆動回路と、前記信号線と前記走査線の交点近傍に
設けられたスイッチング素子と、前記スイッチング素子
に接続された画素電極と、前記走査線と対になり概平行
配置された共通電極線と、前記画素電極に一端を接続し
他端は前記共通電極線に接続された保持容量と、前記共
通電極線を駆動する共通電極線駆動回路と、前記第1の
基板と液晶層を介して対峙するコモン電極を持つ第2の
基板とからなり、前記画素電極が反射型電極であること
を特徴とする液晶表示装置。
17. A plurality of signal lines provided on a first substrate, a signal line driving circuit for driving the signal lines, a plurality of scanning lines orthogonal to the signal lines, and driving the scanning lines. A scanning line driving circuit, a switching element provided near an intersection of the signal line and the scanning line, a pixel electrode connected to the switching element, and a common electrode line paired with the scanning line and arranged substantially in parallel with the scanning line A storage capacitor connected to the pixel electrode at one end and the other end connected to the common electrode line, a common electrode line driving circuit for driving the common electrode line, and the first substrate and the liquid crystal layer. A liquid crystal display device comprising a second substrate having a common electrode facing each other, wherein the pixel electrode is a reflective electrode.
【請求項18】前記共通電極線駆動回路は前記走査線駆
動回路と同期しかつ出力が2値であることを特徴とする
請求項17記載の液晶表示装置。
18. The liquid crystal display device according to claim 17, wherein said common electrode line driving circuit is synchronized with said scanning line driving circuit and has a binary output.
【請求項19】前記共通電極線駆動回路の2値の出力う
ち片方が可変であることを特徴とする請求項18記載の
液晶表示装置。
19. A liquid crystal display device according to claim 18, wherein one of binary outputs of said common electrode line drive circuit is variable.
【請求項20】前記信号線駆動回路がディジタル信号入
力であることを特徴とする請求項19記載の液晶表示装
置。
20. The liquid crystal display device according to claim 19, wherein said signal line drive circuit is a digital signal input.
【請求項21】前記共通電極線駆動回路の出力のうち、
片方ないし両方が抵抗を介して固定電源に接続されたこ
とを特徴とする請求項18記載の液晶表示装置。
21. An output of the common electrode line driving circuit,
19. The liquid crystal display device according to claim 18, wherein one or both are connected to a fixed power supply via a resistor.
【請求項22】前記共通電極線駆動回路の出力には平滑
コンデンサが接続されていないことを特徴とする請求項
18記載の液晶表示装置。
22. The liquid crystal display device according to claim 18, wherein a smoothing capacitor is not connected to an output of said common electrode line driving circuit.
【請求項23】前記走査線駆動回路と前記共通電極線駆
動回路が多結晶シリコンを用い、かつ第1の基板上に形
成されていることを特徴とする請求項17記載の液晶表
示装置。
23. The liquid crystal display device according to claim 17, wherein said scanning line driving circuit and said common electrode line driving circuit are formed of polycrystalline silicon and formed on a first substrate.
【請求項24】前記走査線駆動回路と前記共通電極線駆
動回路が非晶質シリコンを用い、かつ第1の基板上に形
成されていることを特徴とする請求項17記載の液晶表
示装置。
24. The liquid crystal display device according to claim 17, wherein said scanning line driving circuit and said common electrode line driving circuit are made of amorphous silicon and formed on a first substrate.
【請求項25】前記走査線駆動回路と前記共通電極線駆
動回路が単結晶シリコンを用い、かつ第1の基板上に形
成されていることを特徴とする請求項17記載の液晶表
示装置。
25. The liquid crystal display device according to claim 17, wherein said scanning line driving circuit and said common electrode line driving circuit are formed of single crystal silicon and formed on a first substrate.
【請求項26】前記共通電極線駆動回路は前記走査線駆
動回路と同期しかつ出力が画素電極に正のバイアス電圧
を与えるa値のパルスと画素電極に負のバイアス電位を
与えるb値のパルスからなり、大部分の期間は一定のc
値である3値からなり、a値とb値は固定電源から抵抗
を通じて与えられることを特徴とする請求項17記載の
液晶表示装置。
26. The common electrode line driving circuit synchronizes with the scanning line driving circuit and outputs a pulse having an a value giving a positive bias voltage to the pixel electrode and a pulse having a b value giving a negative bias potential to the pixel electrode. Consisting of a constant c
18. The liquid crystal display device according to claim 17, wherein the liquid crystal display device comprises three values, and the a value and the b value are provided from a fixed power supply through a resistor.
【請求項27】前記共通電極線駆動回路の出力には平滑
コンデンサが接続されていないことを特徴とする請求項
26記載の液晶表示装置。
27. The liquid crystal display device according to claim 26, wherein a smoothing capacitor is not connected to an output of said common electrode line driving circuit.
JP25522899A 1999-09-09 1999-09-09 Liquid crystal display device and driving method Expired - Fee Related JP3402277B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25522899A JP3402277B2 (en) 1999-09-09 1999-09-09 Liquid crystal display device and driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25522899A JP3402277B2 (en) 1999-09-09 1999-09-09 Liquid crystal display device and driving method

Publications (2)

Publication Number Publication Date
JP2001083943A true JP2001083943A (en) 2001-03-30
JP3402277B2 JP3402277B2 (en) 2003-05-06

Family

ID=17275821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25522899A Expired - Fee Related JP3402277B2 (en) 1999-09-09 1999-09-09 Liquid crystal display device and driving method

Country Status (1)

Country Link
JP (1) JP3402277B2 (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924824B2 (en) 2000-01-14 2005-08-02 Matsushita Electric Industrial Co., Ltd. Active matrix display device and method of driving the same
JP2008070880A (en) * 2006-09-14 2008-03-27 Samsung Electronics Co Ltd Display device and storage driving circuit of the same
WO2008114479A1 (en) 2007-03-16 2008-09-25 Sharp Kabushiki Kaisha Liquid crystal display device, and its driving method
JP2008287132A (en) * 2007-05-21 2008-11-27 Epson Imaging Devices Corp Electro-optical device, driving circuit for the electro-optical device, and electrical equipment
WO2009084280A1 (en) 2007-12-28 2009-07-09 Sharp Kabushiki Kaisha Display driving circuit, display device, and display driving method
WO2010032526A1 (en) * 2008-09-16 2010-03-25 シャープ株式会社 Display driving circuit, display apparatus and display driving method
WO2010146742A1 (en) 2009-06-17 2010-12-23 シャープ株式会社 Display driving circuit, display device and display driving method
WO2010146744A1 (en) 2009-06-17 2010-12-23 シャープ株式会社 Display driving circuit, display device and display driving method
US7928941B2 (en) 2007-03-20 2011-04-19 Sony Corporation Electro-optical device, driving circuit and electronic apparatus
WO2011045954A1 (en) 2009-10-16 2011-04-21 シャープ株式会社 Display driving circuit, display device, and display driving method
WO2011045955A1 (en) 2009-10-16 2011-04-21 シャープ株式会社 Display driving circuit, display device, and display driving method
WO2011048843A1 (en) 2009-10-20 2011-04-28 シャープ株式会社 Display apparatus
US8013850B2 (en) 2006-09-01 2011-09-06 Sony Corporation Electrooptic device, driving circuit, and electronic device
US8035634B2 (en) 2006-08-10 2011-10-11 Sony Corporation Electro-optical device, driving circuit, and electronic apparatus
US8305369B2 (en) 2007-10-16 2012-11-06 Sharp Kabushiki Kaisha Display drive circuit, display device, and display driving method
US8558828B2 (en) 2006-09-01 2013-10-15 Japan Display West, Inc. Electrooptic device, driving circuit, and electronic device
US8587572B2 (en) 2007-12-28 2013-11-19 Sharp Kabushiki Kaisha Storage capacitor line drive circuit and display device
US8675811B2 (en) 2007-12-28 2014-03-18 Sharp Kabushiki Kaisha Semiconductor device and display device
US8718223B2 (en) 2007-12-28 2014-05-06 Sharp Kabushiki Kaisha Semiconductor device and display device
US8780017B2 (en) 2009-06-17 2014-07-15 Sharp Kabushiki Kaisha Display driving circuit, display device and display driving method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010016224A1 (en) 2008-08-05 2010-02-11 シャープ株式会社 Liquid crystal display device and method for manufacturing the same

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924824B2 (en) 2000-01-14 2005-08-02 Matsushita Electric Industrial Co., Ltd. Active matrix display device and method of driving the same
US8035634B2 (en) 2006-08-10 2011-10-11 Sony Corporation Electro-optical device, driving circuit, and electronic apparatus
US8013850B2 (en) 2006-09-01 2011-09-06 Sony Corporation Electrooptic device, driving circuit, and electronic device
US8558828B2 (en) 2006-09-01 2013-10-15 Japan Display West, Inc. Electrooptic device, driving circuit, and electronic device
JP2008070880A (en) * 2006-09-14 2008-03-27 Samsung Electronics Co Ltd Display device and storage driving circuit of the same
US8773342B2 (en) 2006-09-14 2014-07-08 Samsung Display Co., Ltd. Display device and storage driving circuit for driving the same
WO2008114479A1 (en) 2007-03-16 2008-09-25 Sharp Kabushiki Kaisha Liquid crystal display device, and its driving method
US8194018B2 (en) 2007-03-16 2012-06-05 Sharp Kabushiki Kaisha Liquid crystal display device and method for driving same
US7928941B2 (en) 2007-03-20 2011-04-19 Sony Corporation Electro-optical device, driving circuit and electronic apparatus
JP2008287132A (en) * 2007-05-21 2008-11-27 Epson Imaging Devices Corp Electro-optical device, driving circuit for the electro-optical device, and electrical equipment
JP4670834B2 (en) * 2007-05-21 2011-04-13 エプソンイメージングデバイス株式会社 ELECTRO-OPTICAL DEVICE, ELECTRIC OPTICAL DEVICE DRIVE CIRCUIT, AND ELECTRIC DEVICE
US8305369B2 (en) 2007-10-16 2012-11-06 Sharp Kabushiki Kaisha Display drive circuit, display device, and display driving method
US8675811B2 (en) 2007-12-28 2014-03-18 Sharp Kabushiki Kaisha Semiconductor device and display device
US8547368B2 (en) 2007-12-28 2013-10-01 Sharp Kabushiki Kaisha Display driving circuit having a memory circuit, display device, and display driving method
WO2009084280A1 (en) 2007-12-28 2009-07-09 Sharp Kabushiki Kaisha Display driving circuit, display device, and display driving method
US8718223B2 (en) 2007-12-28 2014-05-06 Sharp Kabushiki Kaisha Semiconductor device and display device
US8587572B2 (en) 2007-12-28 2013-11-19 Sharp Kabushiki Kaisha Storage capacitor line drive circuit and display device
WO2010032526A1 (en) * 2008-09-16 2010-03-25 シャープ株式会社 Display driving circuit, display apparatus and display driving method
US8531443B2 (en) 2008-09-16 2013-09-10 Sharp Kabushiki Kaisha Display driving circuit, display device, and display driving method
WO2010146742A1 (en) 2009-06-17 2010-12-23 シャープ株式会社 Display driving circuit, display device and display driving method
WO2010146744A1 (en) 2009-06-17 2010-12-23 シャープ株式会社 Display driving circuit, display device and display driving method
US8780017B2 (en) 2009-06-17 2014-07-15 Sharp Kabushiki Kaisha Display driving circuit, display device and display driving method
US8890856B2 (en) 2009-06-17 2014-11-18 Sharp Kabushiki Kaisha Display driving circuit, display device and display driving method
US8933918B2 (en) 2009-06-17 2015-01-13 Sharp Kabushiki Kaisha Display driving circuit, display device and display driving method
WO2011045954A1 (en) 2009-10-16 2011-04-21 シャープ株式会社 Display driving circuit, display device, and display driving method
WO2011045955A1 (en) 2009-10-16 2011-04-21 シャープ株式会社 Display driving circuit, display device, and display driving method
US8797310B2 (en) 2009-10-16 2014-08-05 Sharp Kabushiki Kaisha Display driving circuit, device and method for polarity inversion using retention capacitor lines
US9218775B2 (en) 2009-10-16 2015-12-22 Sharp Kabushiki Kaisha Display driving circuit, display device, and display driving method
WO2011048843A1 (en) 2009-10-20 2011-04-28 シャープ株式会社 Display apparatus

Also Published As

Publication number Publication date
JP3402277B2 (en) 2003-05-06

Similar Documents

Publication Publication Date Title
JP2001083943A (en) Liquid crystal display device and drive method
JP4137394B2 (en) Display device drive method, display device using the same, and portable device equipped with the display device
US6784863B2 (en) Active matrix liquid crystal display and method of driving the same
US6795066B2 (en) Display apparatus and driving method of same
JP4800381B2 (en) Liquid crystal display device and driving method thereof, television receiver, liquid crystal display program, computer-readable recording medium recording liquid crystal display program, and driving circuit
JP3766926B2 (en) Display device driving method, display device using the same, and portable device
US7737935B2 (en) Method of driving liquid crystal display device
JP3534086B2 (en) Driving method of liquid crystal display device
JP4969043B2 (en) Active matrix display device and scanning side drive circuit thereof
KR101260838B1 (en) Liquid crystal display device
CN102339591A (en) Liquid crystal display and method for driving the same
CN108319049B (en) Liquid crystal display and driving method thereof
JP2008233925A (en) Method for driving display device, display device using same and portable device mounted with display device
JP3305931B2 (en) Liquid crystal display
TW200417974A (en) Liquid crystal display
JP2003202546A (en) Driving method and device for liquid crystal display device
JPH07181927A (en) Image display device
JP2000221932A (en) Liquid crystal display device and its driving method
KR101264703B1 (en) LCD and drive method thereof
JPH06266315A (en) Liquid crystal display device
KR101034943B1 (en) Liquid crystal display device and driving method thereof
JP2001296554A (en) Liquid crystal display device and information portable equipment
JP3481349B2 (en) Image display device
JP4801848B2 (en) Liquid crystal display
US20020126081A1 (en) Liquid crystal display device and method for driving the same

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
R151 Written notification of patent or utility model registration

Ref document number: 3402277

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080229

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090228

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100228

Year of fee payment: 7

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100228

Year of fee payment: 7

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100228

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110228

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120229

Year of fee payment: 9

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120229

Year of fee payment: 9

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130228

Year of fee payment: 10

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130228

Year of fee payment: 10

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140228

Year of fee payment: 11

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees