KR100446389B1 - Automatic mode detection circuit of liquid crystal display device, especially including input signal counting unit and signal check unit and selection signal generation unit and mode selection unit - Google Patents

Abstract

PURPOSE: An automatic mode detection circuit of a liquid crystal display device is provided, which selects a proper mode automatically by discriminating several modes using an auto detection circuit and thus remove initial start noise. CONSTITUTION: According to the automatic mode detection circuit for a liquid crystal display device to select one of a data enable only mode and a dual mode, an input signal counting unit(12) counts an input signal inputted normally. A signal check unit(14) checks whether the input signal is inputted normally, by receiving an output signal of the input signal counting unit. A selection signal generation unit(16) generates a mode selection signal by receiving a signal generated in the signal check unit. And a mode selection unit(18) receives the data enable only mode or the dual mode signal, and selects one of the data enable only mode or the dual mode according to the mode selection signal being output from the selection signal generation unit.

Description

Mode automatic detection circuit of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a mode automatic detection circuit capable of automatically selecting one of a data enable or idle mode and a data enable / sync mode depending on whether a vertical synchronous signal is input.

Currently, the signals input to LCD modules from laptop personal computers include data enable only mode and data enable / sync mode.

However, the conventional LCD module has the inconvenience of having to manually select the mode of the input signal according to the type of these input signals. That is, in the related art, the LCD module is designed to operate in only one input mode, so that a laptop personal computer supporting another mode may be applied only by modifying a circuit.

Accordingly, an object of the present invention is to provide a mode automatic detection and startup noise canceling circuit which can identify various input modes using an automatic detection circuit and automatically select a suitable mode.

Another object of the present invention is to provide a mode automatic detection and startup noise removal circuit that can remove several cycles from initial startup to normal operation after initial startup.

1 is a block diagram of a mode automatic detection circuit according to an embodiment of the present invention.

2 is a detailed circuit diagram of a mode automatic detection and startup noise cancellation circuit in accordance with an embodiment of the present invention.

3A to 3B are waveform diagrams illustrating input signals according to an embodiment of the present invention.

4A to 4G are signal waveform diagrams related to a detection circuit according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

12: input signal counting unit 14: signal check unit

16: selection signal generator 18: mode selector

222,224,226,228 and 262: D-flip flop

242: end gate 282: multiplexer

In order to achieve the above object of the present invention, according to an embodiment of the present invention, the mode automatic selection circuit for a liquid crystal display device for selecting one of the data recall mode and the dual mode, counting the input signal normally input; An input signal counting unit; A signal checker which determines whether an input signal is normally input by inputting an output signal of the input signal counting unit; A selection signal generator for generating a mode selection signal by inputting the signal generated by the signal checker; And a mode selector configured to output one of the data enable ounction mode or the dual mode according to the mode selection signal output from the selection signal generator.

The input signal is a vertical synchronization signal when the input signal counting unit operates with the data enable / synchronous signal mode as a priority, and is vertical when the data enable only mode is operated with the priority. A data enable signal having a synchronous signal component, wherein the input signal counting unit is an asynchronous counter circuit, and the signal check unit is configured with a logic gate for logically combining the output signal of the input signal counting unit. The initial reset signal is a clear signal, the output signal of the signal check unit is a clock signal, a high supply voltage is applied as an input signal, and the mode selector is a data input mode signal and a dual mode signal as two inputs. It is preferable that the data selector selects and outputs one of the two inputs.

According to the present invention, an end gate combining four D-flip flops and an output signal of each flip flop is configured to be recognized by the circuit six cycles after Vsync from the input start point. The initial noise of the circuit can be removed by configuring the start noise to be ignored after the first start and the signal is recognized after the signal has stabilized.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a mode automatic detection circuit according to an embodiment of the present invention.

As shown in FIG. 1, the mode automatic detection circuit includes an input signal counting unit 12 and an input signal counting unit 12 that count a vertical synchronization signal Vsync, which is an input signal normally applied for a predetermined time. Receives an output signal from the controller and determines whether the input signal is normally applied, and inputs a signal check unit 14 for outputting the signal P1 according to the determination result, and a signal P1 generated in the signal check unit 14. When it is determined that the vertical synchronization signal Vsync is input as an input signal, the mode selection signal sop_v in the high state is outputted, and when it is determined that the vertical synchronization signal Vsync has not been input as an input signal, the low signal is output. For example, a signal sop_v that selects one of two modes according to the selection signal generator 16 generating the mode selection signal sop_v of the state and the mode selection signal generated by the selection signal generator 16. Go When the signal is high, the data enable / sync mode is selected. When the signal sop_v generated by the selection signal generator 16 is low, the mode enable unit 18 selects the data enable only mode. .

2 is a detailed circuit diagram of a mode automatic detection and startup noise cancellation circuit according to an embodiment of the present invention. Hereinafter, the configuration and operation of the mode automatic detection and startup noise canceling circuit according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4G.

As shown in FIG. 2, the mode automatic detection circuit includes an input signal counter 12, a signal checker 14, a selection signal generator 16, and a mode selector 18.

Here, the input signal counter 12 has four D-flip flops connected in series, and the outputs Q3, Q2, Q1, and Q0 of the respective D-flip flops 222, 224, 226, and 228 are respectively. It is configured to be applied to the inputs (D3, D2, D1, D0) of its own flip-flop through the inverters (223, 225, 227, 229) of the serves as a counter.

The vertical sync signal Vsync is applied as a clock pulse to the D-flip flop 222 to output a signal Q3 in which the vertical sync signal Vsync is divided into two, and the vertical sync signal Vsync is divided into two. Output Q3 of flip-flop 222 is applied as the clock pulse of D-flip-flop 224 to output the same two-divided output Q2. In the same manner as the flip-flop 224 of the front-end flip-flop 224 and the D-flip-flop 226, the outputs of the flip-flop of the front end, which are inputted as clock pulses, respectively, are divided in two to output the outputs Q1 and Q0. Export.

In the present embodiment, the counter is configured using four D-flip flops, but the number of flip flops can be adjusted as needed. In addition, although a D-flip flop is used, any flip-flop or other logic element capable of the same function may be used.

Although the case where the input signal is the vertical synchronization signal Vsync has been described as an example, the input signal may be a signal data enable only signal having a blank period recognized as a vertical synchronization signal in addition to the vertical synchronization signal Vsync.

In addition, the signal check unit 14 receives the output signal from the input signal counting unit 12 and determines whether or not the vertical synchronization signal Vsync is input as an input signal after a predetermined time. An end gate 242 having four input signals having the outputs Q3, Q2, Q1 and Q0 of the D-flip flops.

Here, in the end gate 242, two input signals of the four input signals are applied as the input signals of the outputs Q2 and Q0 of the flip-flops 224 and 228 as they are, and the remaining two input signals are the flip-flops 222 and 226. a) the output (Q _3, Q ₁₎ from the consists, to be applied are inverted. Therefore, when the outputs Q3, Q2, Q1, and Q0 of the flip-flops 222 to 228 are 0101, the end gate 242 of the signal checking unit 14 outputs the high output signal P1. Otherwise, the signal P1 in the low state is output.

The selection signal generator 16 receives the signal P1 from the signal checker 14 and generates a selection signal for selecting a mode. The selection signal generator 16 includes a D-flip flop 262. The D-flip-flop 262 inputs the signal P1 generated by the signal checking unit 14 as a clock pulse, an initial reset signal frst is applied to the clear terminal CLEAR, and an input terminal D ), A high supply voltage Vcc is applied.

Since the D-flip flop 262 is always input to the input terminal D with the high supply voltage Vcc, the D-flip flop 262 is initially reset by the initial reset signal frst. When the output P1 of the signal check unit 14 applied to the clock pulse is transitioned from the low state to the high state, its output sop_v becomes high. Then, even if the output P1 of the signal check unit 14 applied as the clock pulse is transitioned from the high state to the low state or from the low state to the high state, the output sop _- v of the D-flip flop 262 is always present. It remains high.

Finally, the mode selector 18 selects two data inputs, that is, a data enableonly signal DE_ONLY_SIGNAL, using the signal sop _- v generated by the select signal generator 16 as a select signal. And a 2x1 multiplexer 282 that selects and outputs only one of a data enable / synchronizing signal (DE_SYNC_SIGNAL).

The mode selector 18 selects DE_SYNC_SIGNAL to operate in a data enable / synchronous mode, that is, a dual mode when the select signal sop _- v applied from the select signal generator 16 is high, and outputs an output drive signal ( OUTPUT_DRIVING_SIGNAL is output to the liquid crystal module. If the selection signal (sop_v) is low, DE_ONLY_SIGNAL is selected to operate in the data enable ounction mode and the output drive signal (OUTPUT_DRIVING_SIGNAL) is output to the liquid crystal module.

Hereinafter, the principle of the two input modes and detection input to the 2x1 MUX 282 of the input signal selection unit 28 will be described.

As a signal input from the outside, for example, from a laptop personal computer is applied differently in each case, there is a need for an LCD module that can be widely applied. However, focusing on the fact that the signal input from the notebook personal computer is two cases, the data enable signal DE and the vertical synchronization signal Vsync, only the requirements of the signal used in each mode can be determined and used.

(1) In case of data enable only mode

In the data enable only mode, as shown in FIG. 3A, the data enable signal has a blank section corresponding to a section recognized as a vertical synchronization signal (Vsync) in the signal itself, and is vertical in itself. It is possible to replace the pulse of the synchronization signal Vsync. Therefore, even if the vertical synchronization signal Vsync1 as shown in FIG. 3A does not come in at the same time, the data enable signal DE1 is a complete signal so that the LCD module can be operated. . In this case, the vertical synchronization signal Vsync1 does not need to be considered, and only the correct data enable signal DE1 is considered.

(2) Dual mode (data enable / vertical sync signal mode)

In the dual mode, as shown in FIG. 3B, unlike the data enable signal DE1 of FIG. 3A, the data enable signal DE2 having no blank section for recognizing the vertical synchronization signal is input. Both the data enable signal DE2 and the vertical synchronization signal Vsync2 are required.

Principle of detection

1. Detecting with priority in dual mode

The circuit operates normally regardless of whether the data enable signal DE has a component of the vertical synchronization signal Vsync. In other words, the vertical synchronization signal Vsync that the data enable signal does not have is input as a separate signal. Therefore, in this case, only the input of the vertical synchronization signal Vsync needs to be detected.

2. Detecting Priority in Data Enable Own Mode

In this case, the presence or absence of Vsync is not considered, and only the data enable signal has a component of the vertical synchronization signal Vsync.

2 is a circuit for automatically detecting a mode by setting a priority to a dual mode.

In the circuit shown in FIG. 2, an operation of detecting a mode with priority as a dual mode will be described with reference to the waveform diagram of FIG.

Initially, a reset signal frst is initially applied to clear all flip-flops 222, 224, 226, 228, and 262. Subsequently, the input signal counting unit 12 starts counting using the vertical synchronization signal Vsync as a clock pulse. When the vertical synchronization signal Vsync as shown in FIG. 4A is applied to the clock pulse of the flip-flop 222, the flip-flop 222 outputs the signal Q ₃ as shown in FIG. 4B in which the vertical synchronization signal Vsync is divided into two. do.

The signal Q ₃ divided by the vertical synchronization signal Vsync is applied to the clock terminal of the next flip-flop 224, and the signal Q ₂ shown in FIG. 4C is further divided. After each flip-flop, the signal at the front end is divided by two. Accordingly, the signals Q ₁ and Q _{0 as} shown in FIG. 4D and FIG. 4E are output through the flip-flop 226 and the flip-flop 228, respectively.

In this way, it is determined whether the input signal is a normal signal at the end gate 242 of the signal checking unit 14 that uses the two-divided signals Q ₃ -Q ₀ as the input signals. For example, as shown in the waveform diagram according to the embodiment of the present invention of FIG. 4, when the vertical synchronization signal Vsync is input, each flip-flop 222, 224, and 226 constituting the input signal counting unit 12 is provided. And the output P1 of the end gate 242 until just before the outputs Q ₃ , Q ₂ , Q ₁ and Q ₀ of 228 become 0, 1, 0, 1, respectively, 6 cycles of the vertical synchronization signal Vsync. Keep low. Once the output of each flip-flop becomes 0, 1, 0, 1, respectively, the output P1 of the end gate 242 of the signal check signal section 14 goes high.

Once the output P1 of the end gate 242 is in the high state, the flip-flop 262 of the select signal generator 16 emits the output sov_p in the high state. The mode selector 18 outputs the output drive signal OUTPUT_DRIVING_SIGNAL from DE_SYNC_SIGNAL for the dual mode operation among the two input signals by the high selection signal sov_p output from the selection signal generator 16.

On the other hand, when the vertical synchronization signal Vsync is not applied, the clock signal is not applied to the flip-flop 222 of the input signal counting unit 12, and thus its output does not change and remains low. Accordingly, the output of the next flip-flops 224-228 is also kept low, and the input signal counting unit 12 outputs the output signals Q ₃ -Q _{0 in the} low state.

The signal discrimination unit 14 which receives the output signal of the input signal counting unit 12 as an input outputs a low signal P1 through the end gate 242. Since the signal P1 in the low state is applied as the clock signal of the flip-flop 262 of the selection signal generator 16, its output sov_p is kept low.

Accordingly, the MUX 282 of the mode selector 18 receives the selection signal in the low state, selects the data enable occurrence signal DE_ONLY_SIGNAL among the two inputs, and outputs it as the output drive signal OUTPUT_DRIVING_SIGNAL.

As described in detail above, the embodiment of the present invention uses an end gate that combines four D-flip flops and the output signal of each flip flop, so that the circuit can be recognized after six cycles of Vsync from the input starting point. Consists of. The initial noise of the circuit can be removed by configuring the start noise to be ignored after the first start and the signal is recognized after the signal has stabilized.

In the present embodiment, although the D-flip flop is used in the input signal counter, various kinds of flip flops having the same role may be used.

In addition, although four flip-flops are used in this embodiment, a circuit is started after a few signals from an input signal first input, for example, a Vsync signal, by using an end gate that combines the number of flip-flops with the output signal of each flip-flop. It can be designed to be recognized by.

In addition, in the present embodiment, the case in which the Vsync signal is used as the input signal has been described, but the priority can be used in the case of the data isolation mode by inputting the data enable signal.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (9)

A mode automatic selection circuit for a liquid crystal display device for selecting one of a data recall mode and a dual mode, An input signal counting unit counting an input signal normally input; A signal checker which determines whether the input signal is normally input by inputting an output signal of the input signal counting unit; A selection signal generator for generating a mode selection signal by inputting the signal generated by the signal checker; And A mode selector configured to receive the data enable occurrence mode or the dual mode signal, and select one of the data enable occurrence mode or the dual mode according to the mode selection signal output from the selection signal generator; A mode automatic detection circuit of a liquid crystal display device, characterized in that. The method of claim 1, wherein the input signal is a vertical synchronization signal when the input signal counting unit operates with the data enable / sync signal mode as the priority, and the data enable only mode is the priority. And a mode enable signal having a vertical synchronizing signal component. 3. The mode automatic detection circuit of a liquid crystal display device according to claim 2, wherein the input signal counting unit is an asynchronous counter circuit. 3. The mode automatic detection circuit of a liquid crystal display device according to claim 2, wherein the signal check unit comprises a logic gate for logically combining the output signal of the input signal counting unit. 3. The liquid crystal display according to claim 2, wherein the selection signal generator is an initial reset signal as a clear signal, the output signal of the signal checker is a clock signal, and a high supply voltage is applied as an input signal. Automatic mode detection circuit of the device. 3. The mode automatic detection circuit of a liquid crystal display device according to claim 2, wherein the mode selector is a data selector for inputting a data isolation mode signal and a dual mode signal into two inputs and selecting one of the two inputs. 4. The asynchronous counter circuit of claim 3, wherein a plurality of flip-flops are connected in series, and the output of each flip-flop is configured to be applied to an input of its own flip-flop through a respective inverter, And the input signal is applied to a flop as a clock pulse. 5. The liquid crystal display device of claim 4, wherein the logic gate is an end gate which inputs outputs of the plurality of flip-flops as input signals and generates a signal obtained by logically multiplying the input signals by the selection signal generator. Automatic detection circuit. 7. The mode automatic detection circuit of a liquid crystal display device according to claim 6, wherein the data purifier is a 2x1 multiplexer having two inputs of a data isolation mode signal and a dual mode signal and selecting one of the two inputs.

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