JPH06259040A - Liquid crystal display controller - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display controller capable of adjusting the display characteristic of a liquid crystal. CONSTITUTION:By a mode selection control part 6, a selection signal according to a set horizontal period is outputted. By a horizontal period clear signal selector 7, any one among counter clear signals from a counter clear decoder 3 is selected according to the selection signal from the mode selection control part 6, and the clear signal is supplied to a horizontal period counter 2 to clear the horizontal period counter 2. By a horizontal synchronizing clear signal selector 8, any one among horizontal off signals from a horizontal synchronizing signal decoder 4 is selected according to the selection signal from the mode selection control part 6 to output it. By a horizontal synchronizing signal generating part 5, a horizontal synchronizing signal is generated synchronizing with a basic clock from a clock supply part 1 according to a horizontal ON signal from the horizontal synchronizing signal decoder 4 and the horizontal OFF signal from the horizontal synchronizing clear signal selector 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display control device for controlling the display of a dot matrix type liquid crystal display panel.

[0002]

2. Description of the Related Art In recent years, in the field of computer display devices, diversification has progressed, and in addition to conventional CRT type display devices, there has been an increasing need for downsized and low-power computers, which have made them thinner and save power. Type dot matrix type liquid crystal panel display devices have become popular. In the case of liquid crystal as well, similar to the CRT, the display is controlled by inputting a synchronizing signal suitable for each panel.

A conventional liquid crystal display control device for controlling the display of such a dot matrix type liquid crystal panel is, as shown in FIG. 6, a clock supply section 31 and a horizontal cycle counter 32.
The counter clear decoder 33, the horizontal sync signal decoder 34, and the horizontal sync signal generator 35 are provided.
The clock supply unit 31 outputs a basic clock for generating a horizontal synchronization signal. The horizontal cycle counter 32 counts the basic clock from the clock supply unit 31.
The counter clear decoder 33 includes a horizontal cycle counter 32.
When the output count value of 1 reaches a predetermined value corresponding to the horizontal cycle, the horizontal cycle counter 32 is cleared. The horizontal synchronization signal decoder 34 sends a horizontal ON signal and a vertical OFF signal to the horizontal synchronization signal generator 35 when the output count value of the horizontal cycle counter 32 reaches a predetermined value corresponding to the beginning and end of the ON period of the horizontal synchronization signal. Is output. The horizontal sync signal generator 35 generates a horizontal sync signal in synchronization with the basic clock from the clock supplier 31 based on the horizontal ON signal and the vertical OFF signal from the horizontal sync signal decoder 34.

FIG. 7 is a waveform diagram of a horizontal synchronizing signal created by a conventional liquid crystal display control device. In this conventional liquid crystal display control device, the horizontal cycle counter 32 counts the basic clock from the clock supply unit 31 and counts up from the count value 0. Then, the counter clear decoder 33 monitors the count value of the horizontal cycle counter 32, and when the count value reaches a count value corresponding to a preset horizontal cycle, a one-shot width one-shot pulse is used as a counter clear signal to perform horizontal scanning. It outputs to the cycle counter 32 and clears the horizontal cycle counter 32. As a result, the horizontal period H of the horizontal synchronizing signal shown in FIG. 7 is determined. Then, the horizontal synchronization signal decoder 34 monitors the count value of the horizontal cycle counter 32 similarly to the counter clear decoder 33, and when it reaches a predetermined value corresponding to the beginning and end of the preset ON period of the horizontal synchronization signal, respectively. A one-shot pulse having a one-clock width is supplied to the horizontal synchronizing signal generator 35 as a horizontal ON signal and a horizontal OFF signal. As a result, the ON period of the horizontal synchronizing signal in FIG. 7, that is, the horizontal blank period A is determined. Then, a horizontal synchronizing signal generator 3 including a JK flip-flop
5, the horizontal ON signal and the horizontal OFF signal from the horizontal synchronizing signal decoder 34, that is, the one-shot pulses representing the beginning and end of the ON period of the horizontal synchronizing signal are supplied to the J and K input terminals, respectively, and the clock is supplied. A horizontal synchronization signal as shown in FIG. 7 is created in synchronization with the basic clock from the supply unit 31. In the liquid crystal panel, this horizontal synchronizing signal is used as a signal for starting data transfer to an internal horizontal liquid crystal driver or a signal for horizontal blanking.

[0005]

However, in the above-described conventional configuration, since the horizontal period H can be set only once, the vertical period is also uniquely determined, and the display characteristics of the liquid crystal panel are fixed. These LCD panels are
Unlike the CRT, the sync signal for display is not uniquely determined. For example, the cycle of the vertical sync signal is 6
Many of them have a flexible regulation of 0 to 70 Hz. Further, in the case of a liquid crystal panel, the vertical period depends on the characteristics of contrast and response speed in addition to the adjustment of the liquid crystal device during manufacturing. FIG. 8 shows an example of a characteristic diagram showing the relationship between the vertical period and the response speed and contrast in the STN type liquid crystal panel. The liquid crystal panel is required to have a high response speed and a high contrast, but it is clear from the characteristic diagram of FIG. 8 that the response speed becomes faster but the contrast becomes darker and the vertical cycle becomes longer as the vertical period becomes larger. If is small, the contrast becomes bright but the response speed becomes slow, so it is difficult to set the optimum vertical period.
That is, the conventional liquid crystal display control device has a problem that the characteristics of contrast and response speed cannot be changed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal display control device capable of adjusting the display characteristics of liquid crystal.

[0007]

According to a first aspect of the present invention, there is provided a clock supply section for outputting a basic clock for generating a horizontal synchronizing signal, and a basic clock from the clock supply section is counted to output a count value. A horizontal cycle counter, a counter clear decoder that outputs a counter clear signal when the count value from the horizontal cycle counter reaches a plurality of predetermined values, and the count value from the horizontal cycle counter is a first predetermined value. A horizontal synchronizing signal decoder is provided which outputs a horizontal ON signal when reaching a value and outputs a horizontal OFF signal when the count value from the horizontal period counter reaches a plurality of second predetermined values. A mode selection control unit that outputs a selection signal according to the horizontal cycle, and the counter based on the selection signal from the mode selection control unit. A horizontal cycle clear signal selector for selecting any one of the counter clear signals from the clear decoder and supplying the counter clear signal to the horizontal cycle counter to clear the horizontal cycle counter; and the mode selection control section. A horizontal sync clear signal selector for selecting and outputting any one of the horizontal off signals from the horizontal sync signal decoder based on the selection signal, and a horizontal on signal from the horizontal sync signal decoder and the horizontal sync signal. A horizontal sync signal generator that generates a horizontal sync signal in synchronization with the basic clock from the clock supply unit based on the horizontal off signal from the clear signal selector;
It is characterized by having.

According to a second aspect of the present invention, there is provided a clock supply section for outputting a basic clock for generating a horizontal synchronizing signal, and a horizontal cycle counter for counting the basic clock from the clock supply section and outputting a count value. A horizontal sync signal decoder that outputs a horizontal ON signal when the count value from the horizontal cycle counter reaches a predetermined value, a register set control unit that outputs a setting signal according to the set horizontal cycle, and this register set. A horizontal period setting register set to a value based on a setting signal from the control unit; a horizontal synchronization signal setting register set to a value based on the setting signal from the register set control unit; and a horizontal period setting register from the horizontal period counter. When the count value and the setting value of the horizontal cycle setting register match, a counter clear signal is output to output the horizontal cycle counter. A horizontal cycle clear comparator that clears the input signal, a horizontal sync clear comparator that outputs a horizontal off signal when the count value from the horizontal cycle counter and the set value of the horizontal sync signal setting register match, and the horizontal sync signal A horizontal synchronization signal generator that generates a horizontal synchronization signal in synchronization with the basic clock from the clock supply unit based on a horizontal ON signal from the decoder and a horizontal OFF signal from the horizontal synchronization clear comparator. It is characterized by that.

According to a third aspect of the present invention, there is provided a clock supply section for outputting a basic clock for generating a horizontal synchronizing signal, and a horizontal cycle counter for counting the basic clock from the clock supply section and outputting a count value. A horizontal sync signal decoder that outputs a horizontal ON signal when the count value from the horizontal cycle counter reaches a predetermined value, a register set control unit that outputs a setting signal according to the set horizontal cycle, and this register set. A horizontal synchronization signal setting register that is set to a value based on a setting signal from the control unit,
When the horizontal cycle setting adder that outputs a value obtained by adding a predetermined value to the setting value of the horizontal synchronization signal setting register and the count value from the horizontal cycle counter and the output value of the horizontal cycle setting adder match A horizontal cycle clear comparator that outputs a counter clear signal to clear the horizontal cycle counter and a horizontal off signal when the count value from the horizontal cycle counter and the setting value of the horizontal synchronization signal setting register match A horizontal sync signal is generated in synchronization with a basic clock from the clock supply unit based on a horizontal sync clear comparator, a horizontal on signal from the horizontal sync signal decoder, and a horizontal off signal from the horizontal sync clear comparator. And a horizontal synchronizing signal generator.

[0010]

In the invention of claim 1, the clock supply section is
It outputs the basic clock for generating the horizontal sync signal. The horizontal cycle counter counts the basic clock from the clock supply unit and outputs a count value. The counter clear decoder outputs a counter clear signal when the count value from the horizontal period counter reaches a plurality of predetermined values. The horizontal synchronization signal decoder outputs a horizontal ON signal when the count value from the horizontal cycle counter reaches a first predetermined value, and the count value from the horizontal cycle counter reaches a plurality of types of second predetermined values. Sometimes a horizontal off signal is output. The mode selection control unit outputs a selection signal according to the set horizontal cycle. The horizontal cycle clear signal selector selects any one of the counter clear signals from the counter clear decoder based on the selection signal from the mode selection control unit and supplies the counter clear signal to the horizontal cycle counter to horizontally Clear the cycle counter. The horizontal sync clear signal selector
Based on the selection signal from the mode selection control unit, one of the horizontal off signals from the horizontal sync signal decoder is selected and output. The horizontal sync signal generator generates a horizontal sync signal in synchronization with the basic clock from the clock supplier based on the horizontal on signal from the horizontal sync signal decoder and the horizontal off signal from the horizontal sync clear signal selector.

In the invention of claim 2, the clock supply section outputs a basic clock for generating a horizontal synchronizing signal. The horizontal cycle counter counts the basic clock from the clock supply unit and outputs a count value. The horizontal synchronizing signal decoder outputs a horizontal ON signal when the count value from the horizontal cycle counter reaches a predetermined value. The register set control unit outputs a setting signal according to the set horizontal cycle. The horizontal cycle setting register is set to a value based on the setting signal from the register set control unit.
The horizontal synchronization signal setting register is set to a value based on the setting signal from the register set control unit. The horizontal cycle clear comparator outputs a counter clear signal to clear the horizontal cycle counter when the count value from the horizontal cycle counter and the set value of the horizontal cycle setting register match. The horizontal sync clear comparator outputs a horizontal off signal when the count value from the horizontal cycle counter and the set value of the horizontal sync signal setting register match. The horizontal synchronization signal generation unit generates a horizontal synchronization signal in synchronization with the basic clock from the clock supply unit based on the horizontal ON signal from the horizontal synchronization signal decoder and the horizontal OFF signal from the horizontal synchronization clear comparator.

In the invention of claim 3, the clock supply section outputs a basic clock for generating the horizontal synchronizing signal. The horizontal cycle counter counts the basic clock from the clock supply unit and outputs a count value. The horizontal synchronizing signal decoder outputs a horizontal ON signal when the count value from the horizontal cycle counter reaches a predetermined value. The register set control unit outputs a setting signal according to the set horizontal cycle. The horizontal synchronization signal setting register is set to a value based on the setting signal from the register set control unit. The horizontal period setting adder outputs a value obtained by adding a predetermined value to the setting value of the horizontal synchronization signal setting register. The horizontal cycle clear comparator outputs a counter clear signal to clear the horizontal cycle counter when the count value from the horizontal cycle counter and the output value of the horizontal cycle setting adder match. The horizontal sync clear comparator outputs a horizontal off signal when the count value from the horizontal cycle counter and the set value of the horizontal sync signal setting register match. The horizontal synchronization signal generation unit generates a horizontal synchronization signal in synchronization with the basic clock from the clock supply unit based on the horizontal ON signal from the horizontal synchronization signal decoder and the horizontal OFF signal from the horizontal synchronization clear comparator.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a liquid crystal display control device according to a first embodiment of the present invention. This liquid crystal display control device includes a clock supply unit 1, a horizontal cycle counter 2, a counter clear decoder 3, and a horizontal clear counter 3. A sync signal decoder 4, a horizontal sync signal generator 5, a mode selection controller 6, a horizontal cycle clear signal selector 7, and a horizontal sync clear signal selector 8 are provided. The clock supply unit 1 outputs a basic clock for generating a horizontal synchronization signal. The horizontal cycle counter 2 counts the basic clock from the clock supply unit 1 and outputs a count value. Counter clear decoder 3
Outputs a counter clear signal when the count value from the horizontal cycle counter 2 reaches a plurality of predetermined values. The horizontal synchronization signal decoder 4 outputs a horizontal ON signal when the count value from the horizontal cycle counter 2 reaches a first predetermined value, and the count value from the horizontal cycle counter 2 is a plurality of second predetermined values. When it reaches, the horizontal off signal is output. The horizontal sync signal generator 5 is responsive to the horizontal ON signal from the horizontal sync signal decoder 4 and the horizontal OFF signal from the horizontal sync clear signal selector 8 in synchronization with the basic clock from the clock supplier 1 to generate a horizontal sync signal. To occur. The mode selection control unit 6 outputs a selection signal according to the horizontal cycle set by the operator's selection operation. The horizontal cycle clear signal selector 7 selects any one of the counter clear signals from the counter clear decoder 3 based on the selection signal from the mode selection control unit 6, and outputs the counter clear signal to the horizontal cycle counter 2
To clear the horizontal cycle counter 2. The horizontal sync clear signal selector 8 selects and outputs any one of the horizontal off signals from the horizontal sync signal decoder 4 based on the selection signal from the mode selection control unit 6.

FIG. 2 is a block diagram of a synchronizing signal generator of the liquid crystal display control device. The horizontal cycle counter 2 is composed of a counter, the horizontal synchronizing signal decoder 4 is composed of a counter decoding circuit, and the horizontal synchronizing signal generator 5 is provided. Is a JK flip-flop, the mode selection control unit 6 is a mode selection unit, and the horizontal synchronization clear signal selector 8 is a 4to1 selector.

FIG. 3 is a signal waveform diagram of each part of the synchronizing signal creating part. Next, the operation will be described. When the clock supply unit 1 outputs the basic clock to the horizontal period counter 2 and the horizontal synchronization signal generation unit 5, the horizontal period counter 2 counts the basic clock from the clock supply unit 1 and the count value 0
The count-up operation is performed from. Then, the horizontal synchronization signal decoder 4 decodes the count value of the horizontal cycle counter 2 and outputs a horizontal ON signal that determines the beginning of the ON period of the horizontal synchronization signal when the count value reaches a first predetermined value. Then, when the count value reaches a plurality of types of second predetermined values, the horizontal off signal that determines the end of the on period of the horizontal synchronization signal is output. Now, as shown in FIG. 3, it is assumed that the mode selection control unit 6 is set so that the ON period of the horizontal synchronizing signal, that is, the beginning of the horizontal blank period has the count value 0h and the end thereof has the count value 5h. That is, the horizontal sync signal decoder 4 outputs a one-shot pulse with a count value of 0h to the J input terminal of the horizontal sync signal generator 5 as a horizontal ON signal, and the horizontal sync clear signal selector 8 outputs a one-shot pulse with a count value of 5h. Is selected as the horizontal off signal and is output to the K input terminal of the horizontal synchronizing signal generator 5. Then, the horizontal synchronization signal generator 5
Based on the horizontal ON signal from the horizontal sync signal decoder 4 and the horizontal OFF signal from the horizontal sync clear signal selector 8, a horizontal sync signal with an ON period of 5 clocks is synchronized with the basic clock from the clock supply unit 1. create. On the other hand, the counter clear decoder 3 causes the horizontal cycle counter 2 to
When the count value from reaches a predetermined value of multiple types,
Outputs counter clear signals respectively. Then, the horizontal cycle clear signal selector 7 selects one of the counter clear signals from the counter clear decoder 3 based on the selection signal from the mode selection control unit 6 and outputs it to the horizontal cycle counter 2. As a result, the horizontal cycle counter 2 is cleared. In the case of a liquid crystal panel, the ON period of the horizontal synchronization signal represents a horizontal blank period. In the horizontal synchronization signal of FIG. 3, A is a horizontal blank period, B is a data display period,
H is equal to A + B and represents a horizontal period. Since the vertical cycle is also determined by the horizontal cycle H, the vertical cycle can be changed by changing the horizontal cycle H. Since the data display period B of the horizontal period H is constant and cannot be changed, if the horizontal blank period A irrelevant to the display is changed, the horizontal period H changes and the vertical period can be changed.

When the setting of the mode selection control section 6 is switched by a selection operation, the horizontal sync clear signal selector 8 selects a horizontal end signal from the horizontal sync signal decoder 4 having a value other than 5h. , To the K input terminal of the horizontal synchronizing signal generator 5. As a result, the timing of ending the horizontal blank period A of the horizontal sync signal generated by the horizontal sync signal generator 5 changes. At this time, since the horizontal period H also changes at the same time, the horizontal period clear signal selector 7
However, based on the selection signal from the mode selection control unit 6, an appropriate one of the counter clear signals from the counter clear decoder 3 is selected and output to the horizontal cycle counter 2.

As described above, the clock supply unit 1 which outputs the basic clock for generating the horizontal synchronizing signal, the horizontal cycle counter 2 which counts the basic clock from the clock supply unit 1 and outputs the count value, and the horizontal A counter clear decoder 3 that outputs a counter clear signal when the count value from the cycle counter 2 reaches a plurality of predetermined values, and a counter clear decoder 3 when the count value from the horizontal cycle counter 2 reaches a first predetermined value. A horizontal synchronization signal decoder 4 that outputs a horizontal ON signal and outputs a horizontal OFF signal when the count value from the horizontal cycle counter 2 reaches a plurality of second predetermined values, and The mode selection control unit 6 which outputs the selected selection signal, and the counter clear decoder 3 based on the selection signal from the mode selection control unit 6. One of the Ntakuria signal 1
A horizontal cycle signal selector 7 for selecting one of them and supplying the counter clear signal to the horizontal cycle counter 2 to clear the horizontal cycle counter 2; and a horizontal synchronization signal decoder 4 based on a selection signal from the mode selection control section 6. A horizontal sync signal selector 8 for selecting and outputting any one of the horizontal off signals from the
A horizontal synchronization signal generator 5 for generating a horizontal synchronization signal in synchronization with the basic clock from the clock supply unit 1 based on the horizontal ON signal from the horizontal synchronization signal and the horizontal OFF signal from the horizontal synchronization clear signal selector 8. Therefore, the horizontal period can be arbitrarily changed, and as a result, the vertical period can be arbitrarily changed, so that display characteristics such as contrast and response speed of the liquid crystal can be adjusted. (Embodiment 2) FIG. 4 is a block diagram of a liquid crystal display control device according to a second embodiment of the present invention. This liquid crystal display control device comprises a clock supply unit 11, a horizontal period counter 12, a horizontal period setting register 13, A horizontal sync signal setting register 14,
Horizontal sync signal generator 15 and register set controller 16
A horizontal cycle clear comparator 17, a horizontal sync clear comparator 18, and a horizontal sync signal decoder 19. The clock supply unit 11 outputs a basic clock for generating a horizontal synchronization signal. The horizontal cycle counter 12 counts the basic clock from the clock supply unit 11 and outputs a count value. The horizontal cycle setting register 13 is set to a value based on the setting signal from the register set control unit 16. Horizontal sync signal setting register 1
4 is set to a value based on the setting signal from the register set control unit 16. The horizontal synchronization signal generator 15 generates the horizontal synchronization signal in synchronization with the basic clock from the clock supply unit 11 based on the horizontal ON signal from the horizontal synchronization signal decoder 19 and the horizontal OFF signal from the horizontal synchronization clear comparator 18. Occur. Register set controller 16
Outputs a setting signal according to the horizontal cycle set by the operator's selection operation. Horizontal cycle clear comparator 1
Reference numeral 7 outputs a counter clear signal to clear the horizontal cycle counter 12 when the count value from the horizontal cycle counter 12 and the set value of the horizontal cycle setting register 13 match. The horizontal sync clear comparator 18 outputs a horizontal off signal when the count value from the horizontal cycle counter 12 and the set value of the horizontal sync signal setting register 14 match. The horizontal synchronization signal decoder 19 outputs a horizontal ON signal when the count value from the horizontal cycle counter 12 reaches a predetermined value.

Next, the operation will be described. First, when a desired horizontal period is set in the register set control unit 16 by a selection operation, the register set control unit 16 outputs a setting signal according to the horizontal period to the horizontal period setting register 13. Figure 3
In the above example, a value corresponding to the horizontal period H of the horizontal synchronizing signal is set. Further, the register set control unit 16 sets, in the horizontal synchronizing signal setting register 14, a value corresponding to the end timing of the ON period according to the horizontal cycle. In the example of FIG. 3, a value representing the horizontal blank period A, that is, 5h is set. Then, when the clock supply unit 11 outputs the basic clock to the horizontal period counter 12 and the horizontal synchronization signal generation unit 15, the horizontal period counter 12 counts the basic clock and performs a count-up operation from the count value 0. Then, the horizontal synchronization signal decoder 19 causes the horizontal cycle counter 1
When the count value of 2 reaches a predetermined value, the horizontal ON signal is output to the J input terminal of the horizontal synchronizing signal generator 15. Figure 3
In the example, the one-shot pulse is supplied to the J input terminal of the horizontal synchronizing signal generator 15 when the count value is 0h. Then, the horizontal sync clear comparator 18 outputs a horizontal off signal to the K input terminal of the horizontal sync signal generator 15 when the count value of the horizontal cycle counter 12 and the set value of the horizontal sync signal setting register 14 match. In the example of FIG. 3, the one-shot pulse is supplied to the K input terminal of the horizontal synchronizing signal generator 15 when the count value is 5h. Then, the horizontal cycle clear comparator 17 outputs a counter clear signal to the horizontal cycle counter 12 when the count value of the horizontal cycle counter 12 reaches the set value of the horizontal cycle setting register 13. In the example of FIG. 3, when the value corresponding to the horizontal period H of the horizontal synchronizing signal is reached, a one-shot pulse is supplied to the clear input terminal of the horizontal period counter 12. With the above operation, as in the case of the first embodiment, the horizontal synchronizing signal generator 1
5 produces a horizontal sync signal as shown in FIG. The horizontal cycle H is changed by the selection operation of the register set control unit 16.

As described above, the clock supply unit 11 that outputs the basic clock for generating the horizontal synchronization signal, the horizontal cycle counter 12 that counts the basic clock from the clock supply unit 11 and outputs the count value, and the horizontal A horizontal sync signal decoder 19 that outputs a horizontal ON signal when the count value from the cycle counter 12 reaches a predetermined value, a register set control unit 16 that outputs a setting signal according to the set horizontal cycle, and a register set. The horizontal cycle setting register 13 set to a value based on the setting signal from the control unit 16 and the horizontal synchronization signal setting register 14 set to a value based on the setting signal from the register set control unit 16
And a horizontal cycle clear comparator 17 that outputs a counter clear signal to clear the horizontal cycle counter 12 when the count value from the horizontal cycle counter 12 and the set value of the horizontal cycle setting register 13 match, and the horizontal cycle counter 12 Count value from and horizontal sync signal setting register 1
Based on the horizontal sync clear comparator 18 that outputs a horizontal off signal when the set value of 4 matches, and the horizontal on signal from the horizontal sync signal decoder 19 and the horizontal off signal from the horizontal sync clear comparator 18. Since the horizontal synchronization signal generating unit 15 that generates the horizontal synchronization signal in synchronization with the basic clock from the supply unit 11 is provided, fine control in clock units can be performed by register setting. More precise control can be realized. (Embodiment 3) FIG. 5 is a block diagram of a liquid crystal display control device according to a third embodiment of the present invention. This liquid crystal display control device includes a clock supply unit 21, a horizontal period counter 22, a horizontal period setting adder 23, and a horizontal period setting adder 23. , A horizontal synchronization signal setting register 24,
Horizontal sync signal generator 25 and register set controller 26
A horizontal cycle clear comparator 27, a horizontal sync clear comparator 28, and a horizontal sync signal decoder 29. The clock supply unit 21 outputs a basic clock for generating a horizontal synchronization signal. The horizontal cycle counter 22 counts the basic clock from the clock supply unit 21 and outputs a count value. The horizontal period setting adder 23 outputs a value obtained by adding a predetermined value to the setting value of the horizontal synchronization signal setting register 24. The horizontal sync signal setting register 24 is set to a value based on the setting signal from the register set control unit 26. The horizontal synchronization signal generator 25
Based on the horizontal ON signal from the horizontal sync signal decoder 29 and the horizontal OFF signal from the horizontal sync clear comparator 28, the horizontal sync signal is generated in synchronization with the basic clock from the clock supply unit 21. Register set control unit 26
Outputs a setting signal according to the horizontal cycle set by the operator's selection operation. Horizontal cycle clear comparator 2
Reference numeral 7 outputs a counter clear signal to clear the horizontal cycle counter 22 when the count value from the horizontal cycle counter 22 and the output value of the horizontal cycle setting adder 23 match. The horizontal sync clear comparator 28 outputs a horizontal off signal when the count value from the horizontal cycle counter 22 and the set value of the horizontal sync signal setting register 24 match. The horizontal synchronizing signal decoder 29 outputs a horizontal ON signal when the count value from the horizontal cycle counter 22 reaches a predetermined value.

Next, the operation will be described. First, when a value corresponding to a desired horizontal period is set in the register set control unit 26 by a selection operation, the register set control unit 26 causes the horizontal sync signal setting register 24 to set a value corresponding to the end timing of the ON period of the horizontal sync signal. To set. In the example of FIG. 3, a value representing the horizontal blanking period A of the horizontal synchronizing signal, that is, 5h is set. Then, the clock supply unit 21
The basic clock is output to the horizontal cycle counter 22 and the horizontal synchronization signal generator 25. And the horizontal cycle counter 22
However, the basic clock from the clock supply unit 21 is counted and the count-up operation is performed from the count value 0. Then, the horizontal synchronization signal decoder 29 causes the horizontal cycle counter 22 to
When the count value of 1 reaches a predetermined value, the horizontal ON signal is output to the J terminal of the horizontal synchronizing signal generator 25. In the example of FIG. 3, the one-shot pulse is supplied to the J input terminal of the horizontal synchronizing signal generator 25 when the count value is 0h. Then, the horizontal sync clear comparator 28 outputs a horizontal off signal to the K input terminal of the horizontal sync signal generator 25 when the count value of the horizontal cycle counter 22 and the set value of the horizontal sync signal setting register 24 match. In the example of FIG. 3, the one-shot pulse is supplied to the K input terminal of the horizontal synchronizing signal generator 25 when the count value is 5h. Example 2 up to this point
It is the same operation as. And the horizontal cycle setting adder 23
However, the value of the number of clocks for the display period B is added to the set value of the horizontal synchronization signal setting register 24, and the value is held. In the example of FIG. 3, the number of clocks corresponds to the period in which the display period B is added to the horizontal blanking period A, which is the same as the horizontal period H. And the horizontal cycle clear comparator 27
However, when the count value of the horizontal cycle counter 22 and the value of the horizontal cycle setting adder 23 match, a counter clear signal is output to the horizontal cycle counter 22 to clear the horizontal cycle counter 22. In the example of FIG. 3, at the end of the horizontal cycle H, a one-shot pulse is supplied to the clear input terminal of the horizontal cycle counter 22. As a result, the horizontal synchronization signal generator 25 synchronizes with the basic clock from the clock supplier 21 based on the horizontal ON signal from the horizontal synchronization signal decoder 29 and the horizontal OFF signal from the horizontal synchronization clear comparator 28. Create a signal.

As described above, the clock supply unit 21 that outputs the basic clock for generating the horizontal synchronizing signal, the horizontal cycle counter 22 that counts the basic clock from the clock supply unit 21 and outputs the count value, and the horizontal A horizontal sync signal decoder 29 that outputs a horizontal ON signal when the count value from the cycle counter 22 reaches a predetermined value, a register set control unit 26 that outputs a setting signal according to the set horizontal cycle, and a register set. A horizontal synchronization signal setting register 24 set to a value based on a setting signal from the control unit 26; a horizontal cycle setting adder 23 that outputs a value obtained by adding a predetermined value to the setting value of the horizontal synchronization signal setting register 24; When the count value from the horizontal cycle counter 22 and the output value of the horizontal cycle setting adder 23 match, a counter clear signal is issued. The horizontal cycle clear comparator 27 that applies a force to clear the horizontal cycle counter 22 and the horizontal sync clear that outputs a horizontal off signal when the count value from the horizontal cycle counter 22 and the set value of the horizontal sync signal setting register 24 match Based on the comparator 28, the horizontal ON signal from the horizontal sync signal decoder 29, and the horizontal OFF signal from the horizontal sync clear comparator 28, a horizontal sync signal that generates a horizontal sync signal in synchronization with the basic clock from the clock supply unit 21. Since the signal generator 25 is provided, fine control in clock units can be performed by register setting, and since there is only one register as compared with the case of the second embodiment, it is simplified from the viewpoint of software. The synchronization signal control can be easily realized.

In each of the above embodiments, the horizontal blanking period A is started from the time point of 0h, but it is not always necessary to have such a configuration.

[0023]

As described above, according to the present invention, a clock supply section for outputting a basic clock for generating a horizontal synchronizing signal and a basic clock from the clock supply section are counted and a count value is output. A horizontal cycle counter, a counter clear decoder that outputs a counter clear signal when the count value from the horizontal cycle counter reaches a plurality of predetermined values, and a count value from the horizontal cycle counter reaches a first predetermined value. And a horizontal sync signal decoder that outputs a horizontal ON signal when the count value from the horizontal cycle counter reaches a plurality of second predetermined values, and a horizontal sync signal decoder that sets the horizontal cycle to the set horizontal cycle. A mode selection control unit that outputs a selection signal according to the
A horizontal cycle in which any one of the counter clear signals from the counter clear decoder is selected based on the selection signal from the mode selection control unit, and the counter clear signal is supplied to the horizontal cycle counter to clear the horizontal cycle counter. The clear signal selector, the horizontal sync clear signal selector for selecting and outputting any one of the horizontal off signals from the horizontal sync signal decoder based on the selection signal from the mode selection control unit, and the horizontal sync signal decoder The horizontal synchronization signal generator that generates the horizontal synchronization signal in synchronization with the basic clock from the clock supply unit based on the horizontal ON signal and the horizontal OFF signal from the horizontal synchronization clear signal selector. Since the period can be changed arbitrarily, and as a result, the vertical period can be changed arbitrarily, the contrast and response speed of the liquid crystal can be changed. Which display characteristics can be adjusted. Therefore, for example, when using a new liquid crystal panel with uncertain characteristics, it is not necessary to make a large-scale adjustment of the liquid crystal device during the production of the liquid crystal panel after actually creating a test model, and it is possible to reduce the cost. You can freely change the contrast and response speed in the circuit.

Further, a clock supply section for outputting a basic clock for generating a horizontal synchronizing signal, a horizontal cycle counter for counting the basic clock from the clock supply section and outputting a count value, and a count for the horizontal cycle counter A horizontal sync signal decoder that outputs a horizontal ON signal when the value reaches a predetermined value, a register set control unit that outputs a setting signal according to the set horizontal period, and a setting signal from the register set control unit Horizontal cycle setting register, the horizontal sync signal setting register set to a value based on the setting signal from the register set control unit, the count value from the horizontal cycle counter and the setting value of the horizontal cycle setting register When the and match, the horizontal cycle clear comparator which outputs the counter clear signal and clears the horizontal cycle counter , A horizontal sync clear comparator that outputs a horizontal off signal when the count value from the horizontal cycle counter matches the setting value of the horizontal sync signal setting register, and a horizontal on signal and horizontal sync clear from the horizontal sync signal decoder. If a horizontal sync signal generator that generates a horizontal sync signal in synchronization with the basic clock from the clock supply unit based on the horizontal off signal from the comparator is provided, fine control in clock units is possible by register setting. Therefore, more accurate control can be realized.

Further, a clock supply section for outputting a basic clock for generating a horizontal synchronizing signal, a horizontal cycle counter for counting the basic clock from the clock supply section and outputting a count value, and a count for the horizontal cycle counter A horizontal sync signal decoder that outputs a horizontal ON signal when the value reaches a predetermined value, a register set control unit that outputs a setting signal according to the set horizontal period, and a setting signal from the register set control unit The horizontal sync signal setting register that is set to the specified value, the horizontal cycle setting adder that outputs a value obtained by adding a predetermined value to the setting value of the horizontal sync signal setting register, the count value from the horizontal cycle counter, and the horizontal cycle setting A horizontal cycle clear controller that outputs a counter clear signal and clears the horizontal cycle counter when the output value of the adder matches , A horizontal sync clear comparator that outputs a horizontal off signal when the count value from the horizontal cycle counter matches the setting value of the horizontal sync signal setting register, and a horizontal on signal and horizontal sync clear from the horizontal sync signal decoder. If a horizontal sync signal generator that generates a horizontal sync signal in synchronization with the basic clock from the clock supply unit based on the horizontal off signal from the comparator is provided, fine control in clock units is possible with register settings. Further, since the number of registers is one, the software is simplified, and the control of the synchronizing signal can be realized more easily.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a liquid crystal display control device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a synchronization signal creation unit included in the liquid crystal display control device according to the first embodiment of the present invention.

FIG. 3 is a signal waveform diagram of each part of the synchronization signal creation unit included in the liquid crystal display control device according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a liquid crystal display control device in Embodiment 2 of the present invention.

FIG. 5 is a configuration diagram of a liquid crystal display control device in Embodiment 3 of the present invention.

FIG. 6 is a configuration diagram of a conventional liquid crystal display control device.

FIG. 7 is a waveform diagram of a horizontal synchronizing signal.

FIG. 8 is an explanatory diagram of a relationship between a vertical period, a response speed, and a contrast in the STN type liquid crystal panel.

[Explanation of symbols]

 1 Clock Supply Unit 2 Horizontal Cycle Counter 3 Counter Clear Decoder 4 Horizontal Sync Signal Decoder 5 Horizontal Sync Signal Generator 6 Mode Selection Control Unit 7 Horizontal Cycle Clear Signal Selector 8 Horizontal Sync Clear Signal Selector 11 Clock Supply Unit 12 Horizontal Cycle Counter 13 Horizontal Cycle setting register 14 Horizontal sync signal setting register 15 Horizontal sync signal generation section 16 Register set control section 17 Horizontal cycle clear comparator 18 Horizontal sync clear comparator 19 Horizontal sync signal decoder 21 Clock supply section 22 Horizontal cycle counter 23 Horizontal cycle setting adder 24 Horizontal sync signal setting register 25 Horizontal sync signal generator 26 Register set controller 27 Horizontal cycle clear comparator 28 Horizontal sync clear comparator 29 Horizontal sync signal decoder

Claims (3)

[Claims] 1. A clock supply unit that outputs a basic clock for generating a horizontal synchronization signal, a horizontal cycle counter that counts the basic clock from the clock supply unit and outputs a count value, and a horizontal cycle counter from the horizontal cycle counter. A counter clear decoder that outputs a counter clear signal when each count value reaches a plurality of predetermined values, and a horizontal ON signal when the count value from the horizontal cycle counter reaches a first predetermined value Then, a horizontal synchronizing signal decoder which outputs a horizontal off signal when the count value from the horizontal cycle counter reaches a plurality of types of second predetermined values, and a selection signal corresponding to the set horizontal cycle are output. A mode selection control unit, and a counter from the counter clear decoder based on a selection signal from the mode selection control unit. A horizontal cycle clear signal selector that selects any one of the rear signals and supplies the counter clear signal to the horizontal cycle counter to clear the horizontal cycle counter; and a selection signal from the mode selection control unit. A horizontal sync clear signal selector for selecting and outputting any one of the horizontal off signals from the horizontal sync signal decoder; a horizontal on signal from the horizontal sync signal decoder; and a horizontal sync clear signal selector from the horizontal sync clear signal selector. A liquid crystal display control device comprising: a horizontal synchronization signal generation unit that generates a horizontal synchronization signal in synchronization with a basic clock from the clock supply unit based on a horizontal off signal. 2. A clock supply unit that outputs a basic clock for generating a horizontal synchronization signal, a horizontal cycle counter that counts the basic clock from the clock supply unit and outputs a count value, and a horizontal cycle counter A horizontal sync signal decoder that outputs a horizontal ON signal when the count value reaches a predetermined value, a register set control unit that outputs a setting signal according to the set horizontal cycle, and a setting from the register set control unit. A horizontal period setting register set to a value based on a signal, a horizontal synchronization signal setting register set to a value based on a setting signal from the register set control unit, a count value from the horizontal period counter and the horizontal When the set value of the cycle setting register matches, a counter clear signal is output to clear the horizontal cycle counter. A horizontal cycle clear comparator, a horizontal sync clear comparator which outputs a horizontal off signal when the count value from the horizontal cycle counter and the set value of the horizontal sync signal setting register match, and the horizontal sync signal decoder A horizontal synchronization signal generator that generates a horizontal synchronization signal in synchronization with a basic clock from the clock supply unit based on a horizontal ON signal and a horizontal OFF signal from the horizontal synchronization clear comparator. Liquid crystal display control device. 3. A clock supply unit that outputs a basic clock for generating a horizontal synchronization signal, a horizontal cycle counter that counts the basic clock from the clock supply unit and outputs a count value, and a horizontal cycle counter from the horizontal cycle counter. A horizontal sync signal decoder that outputs a horizontal ON signal when the count value reaches a predetermined value, a register set control unit that outputs a setting signal according to the set horizontal cycle, and a setting from the register set control unit. A horizontal sync signal setting register that is set to a value based on a signal, a horizontal cycle setting adder that outputs a value obtained by adding a predetermined value to the setting value of the horizontal sync signal setting register, and a count value from the horizontal cycle counter And the output value of the horizontal cycle setting adder match, a counter clear signal is output to stop the horizontal cycle counter. A horizontal cycle clear comparator to be left behind, a horizontal sync clear comparator which outputs a horizontal off signal when the count value from the horizontal cycle counter and the set value of the horizontal sync signal setting register match, and from the horizontal sync signal decoder And a horizontal synchronization signal generator that generates a horizontal synchronization signal in synchronization with the basic clock from the clock supply unit based on the horizontal ON signal from the horizontal synchronization signal and the horizontal OFF signal from the horizontal synchronization clear comparator. Characteristic liquid crystal display control device.