JPS60117773A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60117773A JPS60117773A JP58225815A JP22581583A JPS60117773A JP S60117773 A JPS60117773 A JP S60117773A JP 58225815 A JP58225815 A JP 58225815A JP 22581583 A JP22581583 A JP 22581583A JP S60117773 A JPS60117773 A JP S60117773A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- insulating film
- silicon
- region
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 39
- 230000003647 oxidation Effects 0.000 abstract description 15
- 238000007254 oxidation reaction Methods 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 150000004767 nitrides Chemical class 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000007789 gas Substances 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 4
- 229910000041 hydrogen chloride Inorganic materials 0.000 abstract description 4
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 abstract description 4
- -1 boron ions Chemical class 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 210000004907 gland Anatomy 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 （発明の技術分野） 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] (Technical field of invention) The present invention relates to a method for manufacturing a semiconductor device.
（従来技術）
最近の半導体装置は、そのデバイスを使用するシステム
が低消費霜−力を要求する為と部品数をへらす為に、高
速比及び大集積化が進んでいる。この要望？Ｉ−満たす
為の一手段として、集積注入論理回路（Ｉｎｔｅｇｒａ
ｔｅｄ Ｉｎｊｅｃｔｉｏｎ ｈｏｇｉｃ＝以下、ニー
と略記する）が実用化されている。こ゛れは、Ｉ２Ｌが
高密度に集積でき、低消費電力であるという利点を有し
、さらに製造が簡単であるという利点を有しているから
であシ、バイポーラトランジスタや抵抗体と組み合せて
なる複合的なデバイスとして一つの分野を形成している
。(Prior Art) Recent semiconductor devices are becoming increasingly high-speed and highly integrated because systems using the devices require low frost power consumption and reduce the number of components. This request? As a means to meet I-I, integrated injection logic circuits (Integra
ted Injection hogic (hereinafter abbreviated as knee) has been put into practical use. This is because I2L has the advantages of high density integration, low power consumption, and is easy to manufacture, and can be combined with bipolar transistors and resistors. It is forming a field as a complex device.
第１図に従来構造の一例の断面図を示す、１０１はＰ型
基板、１０２はＮｆＪ１埋込層、１０３はＮ型エピタキ
シャル層、１０４はＰ型絶縁層、１０５はインジェクタ
のエミッタおよびコレクタであシ。FIG. 1 shows a cross-sectional view of an example of a conventional structure. 101 is a P-type substrate, 102 is an NfJ1 buried layer, 103 is an N-type epitaxial layer, 104 is a P-type insulating layer, and 105 is an injector emitter and collector. Sh.
さらにＮＰＮ）ランジスタのベース領域、１０６−１は
インジェクタのベース％１０６−２ハＮＰＮトランジス
タのコレクタ、１０６−３はＮ）’Ｎ）ランジスタのエ
ミッタでアシ、そして１０７は電極をそれぞれ示す、か
かる従来の構造では、 ＮＰＮトランジスタはコレクタ
１０６−２．ベース１０５゜エミッタ１０６−３の順に
各領域の面積が小さくなる・しかし、エミッタ１０６−
３とコレクタ１０６−２を逆にして使うＩ２Ｌ では、
エミッタ１０６−３の面積がベース１０５０面積より大
きいと。In addition, 106-1 is the base region of the NPN transistor, 106-1 is the base of the injector, 106-2 is the collector of the NPN transistor, 106-3 is the emitter of the NPN transistor, and 107 is the electrode, respectively. In the structure of the NPN transistor, the collector 106-2. The area of each region becomes smaller in the order of base 105° emitter 106-3. However, emitter 106-
In I2L using 3 and collector 106-2 in reverse,
If the area of emitter 106-3 is larger than the area of base 1050.
ペース１０５からエミ、り１０６−３へ注入される正孔
の数が増加する。この結果、畜積キャリアを放電する為
の時間が増加しさらに電流増巾率が下がる為に、トラン
ジスタの速度が遅くなるという欠点がある。The number of holes injected from the paste 105 to the emitter 106-3 increases. As a result, the time required to discharge the accumulated carriers increases and the current amplification rate decreases, resulting in a disadvantage that the speed of the transistor decreases.
かかる構造上の欠点を改筈する為に提案されている輩ｙ
′従来例を第２図（ａ）〜（ｄ）に示す、すなわち、Ｐ
型半導体基似２０１にＮ＋の埋込層２０２を設け、Ｎ型
エピタキシャル層２０３を成長式せた後に、熱酸化シリ
コン換２０４．チッ化シリコン）１１４２０５． シリ
コン酸化膜２０６を成長させ。The methods proposed to correct such structural defects
'Conventional examples are shown in FIGS. 2(a) to (d), that is, P
After providing an N+ buried layer 202 in the semiconductor substrate 201 and growing an N-type epitaxial layer 203, thermal oxidation silicon conversion 204. silicon nitride) 114205. A silicon oxide film 206 is grown.
分離領域２０７を異方性ドライエ、チング（以下、ＲＩ
Ｅと略記する）で削シ取る（第２図（ａ） ）。The separation region 207 is formed by anisotropic dry etching (hereinafter referred to as RI).
(abbreviated as E) (Fig. 2(a)).
次に、全面に薄い熱酸化シリコン族２０８およびチッ化
シリコン腺を形成し、ＨＩＥによシ側面にのみチッ化膜
２０９を残して長時間の熱処理によシ厚い酸化膜２１０
を形成する（第２図ｆｂ））−エミ、り引き出し以外の
側面の酸化膜２０８とチッ化膜２０９を除去して多結晶
シリコン２１１を全面に成長させ、さらにフォトレジス
ト２１２を塗布し、Ｏ冨プラズマエツチングによシ多結
晶シリコン２１１を産出させて平担する（第２図（Ｃ）
）。Next, a thin thermally oxidized silicon group 208 and a silicon nitride gland are formed on the entire surface, and a thick oxide film 210 is formed by a long-time heat treatment, leaving a nitride film 209 only on the side surface by HIE.
(FIG. 2fb)) - Remove the oxide film 208 and nitride film 209 on the sides other than the emitter and lead-out, grow polycrystalline silicon 211 on the entire surface, and then apply photoresist 212, and Polycrystalline silicon 211 is produced by rich plasma etching and flattened (Fig. 2(C)).
).
その後、レジスト２１２で覆われていない部分り多結晶
シリコンを（ＣＦ’４ ＋ｆ１２ ）ガスで工、チング
し、ボロンをイオン注入して多結晶シリコンの引き出し
電極２１５．Ｐ酸活性ベース領域２１４およびＰ型領域
２１５を形成し、選択酸化により不要の多結晶シリコン
を酸化膜に変え、さらに表面に酸化膜２１９を形成し、
チッ化腺２１３會パッシベーション用に付けた後、コレ
クタ領域およびエミッタ領域を開口して薄い多結晶シリ
コン２１７を付け、ヒ素のイオン注入を行って面談ＵＮ
型領域２２０を形成し、最後にベースコンタクト孔の門
口と金属電極２１８の形成を行う（第２図（ｄ） ）。Thereafter, the portion of the polycrystalline silicon that is not covered with the resist 212 is etched with (CF'4 +f12) gas, boron ions are implanted, and the polycrystalline silicon extraction electrode 215. A P acid active base region 214 and a P type region 215 are formed, unnecessary polycrystalline silicon is changed into an oxide film by selective oxidation, and an oxide film 219 is further formed on the surface.
After attaching the nitride gland 213 for passivation, the collector region and emitter region are opened, a thin polycrystalline silicon layer 217 is attached, and arsenic ions are implanted.
A mold region 220 is formed, and finally the gate of the base contact hole and the metal electrode 218 are formed (FIG. 2(d)).
かかる従来例は、４＃造的には、Ｉ２Ｌ のエミ。Such a conventional example is an I2L emitter in terms of 4# construction.
りとコレクタがほぼ同一面積であって電流増巾率が大き
く取れ、かつエミ、り面積が小さい為にペース２１４か
らエミ、りへの逆注入がへる事と。Since the area of the emitter and the collector are almost the same, a large current amplification rate can be obtained, and since the area of the emitter and the collector is small, back injection from the pace 214 to the emitter and the emitter is reduced.
ペースの引き出し電極２１５が酸化膜で囲まれている為
、活性ベース以外の不要な接合容量が少くなシ高速動作
には優れている。Since the extraction electrode 215 of the paste is surrounded by an oxide film, there is less unnecessary junction capacitance other than the active base, which is excellent for high-speed operation.
しかし、その製造方法としては、次の様ないくつかの欠
点がある。However, this manufacturing method has several drawbacks as follows.
（１）ｇ２図（ａ）に示すように、トランジスタの活性
領域を残して、単結晶をドライエッチする為に側面にダ
メージが残９やすい。(1) As shown in Figure 2 (a), since the single crystal is dry-etched leaving the active region of the transistor intact, damage tends to remain on the side surfaces.
（２）第２図（ｂ）のように、分離領域を選択酸化によ
シ形成する為結晶歪による欠陥を発生させやすい。(2) As shown in FIG. 2(b), since the isolation region is formed by selective oxidation, defects due to crystal distortion are likely to occur.
（３）第２図（Ｃ）のように凹凸面に多結晶シリコン２
１１を成長させる為、選択的に多結晶シリコンを残した
シ除去したシして１表面を平担にする手が非常にむずか
しい０％に、第２図では、レジスト２１２を塗布して凹
部にレジスト２１２を残し、ドライエッチによシ凸部の
多結晶シリコンを除去する方法と示したが、これとて凸
凹がせまい間隔で並んでいれは可能だが、広い凹部があ
ると塗布した時にこの部分のレジストは薄くなりｍｕ＊
プラズマ処理に持たないという欠点がある。このため、
多結晶シリコン２１１の一部をペース電極引き出し以外
の目的で使用した′い場合（例えば抵抗体）に無理を生
ずる・（４）＠２図（ａ）乃至（ｄ）に示されるように
、エピタキシャル成長後にＲＩＢによシ単結晶シリコン
２０３をｓｔ＋ ｒ、その後に単結晶シリコンの選択酸
化と多結晶シリコン２１１の選択酸化を行うが、選択酸
化は高温で長時間処理となる為に、埋込層２０２のエピ
タキシャル、ｒｍ２０３への上方拡散が大きくなってベ
ース領域２１４，２１６との余裕が大きく取れず、この
結果、ＮＰＮ）ランジスタの耐圧が不足する。(3) As shown in Figure 2 (C), polycrystalline silicon 2 is placed on the uneven surface.
In order to grow 11, the remaining polycrystalline silicon was selectively removed to 0%, which is very difficult to flatten the surface. The method described above leaves the resist 212 and removes the polycrystalline silicon on the convex parts by dry etching, but this is possible if the concavities and convexities are lined up at narrow intervals, but if there are wide concave areas, it will be difficult to coat the area. The resist becomes thinner and mu*
The drawback is that it does not hold up to plasma treatment. For this reason,
If you want to use a part of the polycrystalline silicon 211 for a purpose other than drawing out a pace electrode (for example, as a resistor), it will be difficult. (4) @2 As shown in Figures (a) to (d), epitaxial growth Later, the monocrystalline silicon 203 is subjected to ST+R using RIB, and then selective oxidation of the monocrystalline silicon and selective oxidation of the polycrystalline silicon 211 are performed. The upward diffusion into the epitaxial and rm203 becomes large, making it difficult to maintain a large margin with respect to the base regions 214 and 216, resulting in insufficient breakdown voltage of the NPN transistor.
（５）前述したように、工程があまシにも複雑な為。(5) As mentioned above, the process is extremely complex.
高い歩留？維持する事がむずかしい。High yield? Difficult to maintain.
（発明の目的）
本発明の目的は、高速で集積度の高い半導体装置をよシ
答易に作る製造方法を提供することにある。(Objective of the Invention) An object of the present invention is to provide a manufacturing method for easily manufacturing a high-speed, highly integrated semiconductor device.
（発明の構成）
かかる目的を達成する為に、不発明では、基板上に絶縁
膜と多結晶７リコンを積んだ後でＲＩＥによシ開口し、
塩化水素ガス雰囲気中で選択的にエピタキシャル成長を
行い１選択エピタキシャル領域中にトランジスタ領域を
形成する事を特徴とする。(Structure of the Invention) In order to achieve the above object, in the present invention, after stacking an insulating film and polycrystalline silicon on a substrate, opening is performed by RIE,
The method is characterized in that epitaxial growth is selectively performed in a hydrogen chloride gas atmosphere to form a transistor region in one selective epitaxial region.
（実施例） 以下図面を用いて不発明の詳細な説明する。(Example) The invention will be described in detail below with reference to the drawings.
第３図に不発明の一実施例を示す、２Ｍシリコン基板３
０１に層抵抗１０〜３０Ω／口程度のＮ型埋込層３０２
を形成し←第３図（ａ） ） 、絶縁膜３０３を５００
０〜１ｏｏｏｏλ、多結晶シリコン３０４を約５０００
λそれぞれ形成し、熱拡散又はイオン注入によシＰ型不
純物を多結晶シリコン３０４に導入する（第３図（ｂ）
）、選択酸化法によシ、多結晶シリコン３０４を部分
的に絶縁膜３０５に変換せしめた後、熱酸化又はＣＶＤ
法によシ絶縁膜３０６（１
をさら嵯付ける（第３図（Ｃ） ）。FIG. 3 shows an embodiment of the invention, a 2M silicon substrate 3.
01 has an N-type buried layer 302 with a layer resistance of about 10 to 30 Ω/hole.
←Fig. 3(a)), and an insulating film 303 of 500
0~1ooooλ, polycrystalline silicon 304 about 5000
λ, and introduce P-type impurities into the polycrystalline silicon 304 by thermal diffusion or ion implantation (FIG. 3(b)).
), after partially converting the polycrystalline silicon 304 into an insulating film 305 by selective oxidation, thermal oxidation or CVD
An insulating film 306 (1) is further deposited by a method (FIG. 3(C)).
異方性ドライエ、チングによシ、所定の位置に開口を施
して開口部３０７を設ける（第３図（ｄｌ ）。Using an anisotropic dryer and coating, an opening is formed at a predetermined position to form an opening 307 (FIG. 3(dl)).
この場合、多結晶シリコン３０４と絶縁膜３ｏ３゜３０
５．３０６との工、チングレイトが同じである条件を選
んでドライエ、チしてやると、一度で主、チングが終了
するので具合が良い。In this case, polycrystalline silicon 304 and insulating film 3o3°30
If you select a condition where the working and ching rate are the same as 5.306 and do the drying and ching, it will be convenient because the main and ching will be completed in one go.
その後、塩化水素ガスを含む減圧エピタキシャル成長を
行い、開口部３０７に約１【λ−ｃｍの比抵抗のエピタ
キシャル層３０８を絶縁［３０６の高さ程度に選択的に
成長する。エピタキシャル成長前に多結晶シリコンを付
けＲｌＥにょ）開口部３０７の側面に多結晶シリコンを
残してエピタキシャル成長にも良い、こうする事によシ
、エピタキシャル成長した時に表面の平担化は一層優れ
たものになシ、かつＰ型不純物をドープさせた多結晶シ
リコン３０４からのエピタキシャル成長時のオートドー
ピングも軽減される。Thereafter, low-pressure epitaxial growth using hydrogen chloride gas is performed to selectively grow an epitaxial layer 308 having a resistivity of about 1 [λ-cm in the opening 307 to a height of approximately the height of the insulation [306]. It is also good for epitaxial growth by adding polycrystalline silicon before epitaxial growth and leaving polycrystalline silicon on the side surfaces of the opening 307. By doing this, the surface becomes even better when epitaxially grown. Furthermore, autodoping during epitaxial growth from polycrystalline silicon 304 doped with P-type impurities is also reduced.
次に表面を熱酸化又はＣＶＬＪ法によシ絶縁膜３０９を
付け、不安な部分をマスクして、イオン注入法によシボ
ロンを例えは５ＱＫｅｖで１０１０１４ａｔｏ／ｃｍ２
程度打ち込み、トランジスタの活性ベース領域３１２
を形成し、そしてバッシベーＶヨン用のチッ化ＩＪ４３
ｘｏを成長させる。７！！択エビタキ７ヤル成長以後の
熱処理によシ、電極引き出し用多結晶シリコン３０４か
らエピタキシャル領域３０８への側面方向への拡散が生
じ、この結果、イオン注入によシ形成した活性ベース領
域３１２と接続された電極引き出し領域３０４が形成さ
れ、活性ベース領域３１２はこれを通して外部へ電極引
き出しが可能となる（第３図（ｅ） ）。Next, an insulating film 309 is attached to the surface by thermal oxidation or CVLJ method, and unstable parts are masked.
level implant, the active base region 312 of the transistor
and nitride IJ43 for Bassibayon.
Grow xo. 7! ! Due to the heat treatment after selective epitaxial growth, lateral diffusion occurs from the polycrystalline silicon 304 for electrode extraction to the epitaxial region 308, and as a result, it is connected to the active base region 312 formed by ion implantation. An electrode lead-out region 304 is formed, through which electrodes can be drawn out from the active base region 312 (FIG. 3(e)).
次いで、不安の部分をマスクして、絶縁膜３０９゜３１
０をエツチングし、Ｎ型にドープされた多結晶シリコン
３１３を付けるか、又はドープされていない多結晶シリ
コン３１３を成長した後、イオン注入法でヒ素を注入し
熱処理にトランジスタのエミッタ、コレクタ領域３１５
を形成し、ドライエ、チ又はウェットエッチによシネ要
な部分の多結晶シリコンを除去し必要な部分３１３を残
す。Next, the insulating film 309°31 is formed by masking the anxious part.
After etching 0 and attaching N-type doped polycrystalline silicon 313 or growing undoped polycrystalline silicon 313, arsenic is implanted by ion implantation and heat treatment is performed to form the transistor emitter and collector regions 315.
The polycrystalline silicon in the necessary portions of the film is removed by dry etching, etching or wet etching, leaving the necessary portions 313.
最後に電極引き出し用の窓を開はアルミニウム電極３１
４を形成する（第３図（ｆ） ）。Finally, open the window for electrode extraction and open the aluminum electrode 31.
4 (Fig. 3(f)).
以上に述べた製造方法によシ、第１図で示した従来例で
指摘したスピードが遅いという欠点は。The manufacturing method described above does not have the drawback of slow speed, which was pointed out in the conventional example shown in FIG.
トランジスタの活性領域以外が酸化膜３０３，３０５゜
３０６で囲まれる為に寄性答童が減少し、かつ、エミッ
タとコレクタの面積がほぼ等しい為にペースからエミッ
タへの逆注入かへシ、電流増巾率も大きく取れるので高
速化が達成される。Since the area other than the active region of the transistor is surrounded by oxide films 303, 305, and 306, the number of parasitic electrons is reduced, and since the areas of the emitter and collector are almost equal, reverse injection from the paste to the emitter reduces current. Since the amplification rate can also be increased, high speed can be achieved.
しかも、第２図の他の従来例で示した製法上の欠点も、
選択エピタキシャル成長法を使用する事によシ、まず表
面の平担化が容易に出来る事、多結晶シリコン３０４の
選択酸化はエピタキシャル成長前に行っている墨、多結
晶シリコン３０４の下の絶縁膜３０３もエピタキシャル
成長前に行っている墨の為に、埋込層３０２のエピタキ
シャル層３０８への上方拡散が選択酸化とは無関係とな
シ耐圧劣化に対し充分なマージンが取れる。さらに単結
晶シリコン３０８をＲＩＥ又は選択酸化する事が無いの
で、結晶性が良くなシ、さらにまた製造工程が簡単なの
で、従来方法に比較して高い歩留が得られる。Moreover, the drawbacks in the manufacturing method shown in the other conventional example in FIG.
By using the selective epitaxial growth method, first, the surface can be easily flattened, and the selective oxidation of the polycrystalline silicon 304 is performed before epitaxial growth. Because the ink is applied before epitaxial growth, there is a sufficient margin against breakdown voltage deterioration that is unrelated to selective oxidation due to upward diffusion of the buried layer 302 into the epitaxial layer 308. Furthermore, since the single crystal silicon 308 is not subjected to RIE or selective oxidation, the crystallinity is good, and the manufacturing process is simple, so a higher yield can be obtained compared to conventional methods.
第４図を参照して不発明の他の実施例について説明する
。Another embodiment of the invention will be described with reference to FIG.
まず、第３図でボしたように、Ｎ型埋込領域４０２が形
成されたＰ型基板上に酸化膜４０３および多結晶シリコ
ン４０４を成長した後（第４図（ａ）、 （ｂ）ＸＰ型
の不純物を多結晶シリコン４０４に熱拡欣又はイオン注
入によシ導入する。この段、薄い酸化膜４０５’ｆｆｉ
付けた後、ＲＩＥによシ必要な部分に開口部４０６を設
け（第４図（Ｃ） ） 、塩化水素ガスを含む減圧エピ
タキシャル成長によシ選択的にエピタキシャル層４０７
を形成し、さらに１表面に薄い酸化膜４０８．チッ化膜
４０９を付け、多結晶シリコン４ｕ４ｅ＃化映に変換し
たい部分のチ、化膜４０９とぽ化膜４０８をエツチング
して除去する（第４図（ｄ） ）。First, as shown in FIG. 3, after growing an oxide film 403 and polycrystalline silicon 404 on a P-type substrate on which an N-type buried region 402 is formed (FIGS. 4(a) and 4(b)) type impurities are introduced into the polycrystalline silicon 404 by thermal expansion or ion implantation.At this stage, a thin oxide film 405'ffi is introduced.
After the deposition, openings 406 are formed in necessary portions by RIE (FIG. 4(C)), and an epitaxial layer 407 is selectively grown by low pressure epitaxial growth containing hydrogen chloride gas.
A thin oxide film 408. is formed on one surface. A nitride film 409 is applied, and the nitride film 409 and the nitride film 408 in the portion desired to be converted to polycrystalline silicon 4U4E# film are removed by etching (FIG. 4(d)).
その後、高温（９００−１０００℃）で常圧又は加圧に
よる熱酸化によシ多結晶シリコンを酸化ｇ ４１０に選
択的に変換せしめる（第４図ｔｅｌ ）、この後。Thereafter, the polycrystalline silicon is selectively converted into oxidized G410 by thermal oxidation at high temperature (900-1000° C.) under normal pressure or pressure (FIG. 4, tel).
第３図（ｅ）、 （ｆ）に従って素子領域および電極の
形成を行なう。Element regions and electrodes are formed according to FIGS. 3(e) and 3(f).
かかる、第２の実施例によれば、多結晶シリコン４０４
と絶縁膜４０３，４０５をＩ（ＩＥで開口する時に、工
、チングレートの差があっても同じ深さにエツチングで
きるという利点がある。又、ＲＩＥによ多開口した後に
再度多結晶シリコンを付けＲＩＥにより開口部側面にの
み多結晶シリコンを残して選択エピタキシャル成長して
も良い事は＠ｌの実施例と同様である。According to this second embodiment, polycrystalline silicon 404
When opening the insulating films 403 and 405 using IE, there is an advantage that they can be etched to the same depth even if there is a difference in etching rate.Also, after making multiple openings using RIE, polycrystalline silicon is etched again. As in the example of @l, selective epitaxial growth may be performed by leaving polycrystalline silicon only on the side surfaces of the opening by RIE.
なお、第１．第２の実施例共にＰ型、Ｎ型の不純物を逆
転しても良い事は勿論である。また、本発明をＩ２Ｌで
示したが、これに駆足されることはない。In addition, 1. Of course, in the second embodiment, the P-type and N-type impurities may be reversed. Additionally, although the invention has been illustrated as I2L, it is not limited thereto.
第１図は従来例を示す半導体装置の構造断面図である。
１０１・・・・・・Ｐ型基板、１０２・・・・・・Ｎ＋
埋込層。
１０３・・・・・・Ｎｍエピタキシャル層、１０４・・
・・・・Ｐ型分離層、１０５・・・・・・Ｐ型Ｖ）ＮＰ
Ｎ）ランジスタペース及びインジェクタのエミッタ、コ
レクタ、１０６・・・・・・ＮＰＮ）ランジスタのエミ
ッタ及びコレクタ、１０７・・・・・電極、１０８・・
・・・・絶縁膜、第２図（ａ）〜ｆｄｌは他の従来例を
示す製造工程断面図である。
２０１・・・・・・Ｐ型基板、２０２・・・・・・Ｎ
型埋入層、２０３、・・・・Ｎｆｉエピタキシャル層、
２０４・・・・・・絶縁酸化膜、２０５・・・・・・絶
縁チツ化膜、２０６・・・・・・絶縁酸化族、２０７・
・・・・・開口部、２０Ｂ・・・・・・絶縁酸化族、２
０９・・・・・・絶縁チツ化膜、２１０・・・・・・絶
縁酸化膜、２１１・・・・・・多結晶シリコン、２１２
・・・・・７オトレジス）、２１３・・・・・・ノくツ
シベーシ、ン用絶縁チッ化膜、２１４・・・・・・Ｐ型
ＮＰＮ）ランジスタ活性ペース領域、２１５・・・・・
・ボロンドープ多結晶シリコン、２１６・・・・・・Ｐ
型領域、２１７・・・・・・ヒ索ドープ多結晶７リコン
、２１８・・・・・・アルミニウム電極、２１９・・・
・・・絶縁酸化族、第３図（ａ）〜（ｆ）は本発明の第
１の実施例を示す工程断面図である。
３０１・・・・・・Ｐ型基板、３０２・・・・・・Ｎ＋
型埋込層。
３０３・・・・・・絶縁酸化族、３０４・・・・・・多
結晶シリコン、３０５・・・・・・絶縁酸化族、３０６
・・・・・・絶縁酸化１ｌｌ（，３０７・・・・・・開
口部、３０８・・・・・・選択エピタキシャル層、３０
９・・・・・・絶縁酸イヒ膜、３１０・・・・・・絶縁
チッ化課、３１１・・・・・・Ｐ型側面拡散層、３１２
・・・・・・ＰｆｉＮＰＮ）ランジスタ活性ベース領域
。
′３１３・・・・・・ヒ累ドープ多結晶シ１ノコン％
３１４・・・・・・アルミ電極％ ３１５・・・・・・
Ｎ＋型ＮＰＮトランジスタエミッタ及びコレクタ領域。
第４図（ａ）〜（ｅ）は本発明の第２の実施例を示す工
程断面図である・
４０１・・・・・・Ｐ型基板、４０２・・・・・・Ｎ＋
型埋込層。
４０３・・・・・・絶縁酸化族、４０４・・・・・・多
結晶シリコン、４０５・・・・・・絶縁酸化膜、４０６
・・・・・・開口ｍ％４０７・・・・・・選択エピタキ
シャル層、４０８・・・・・・絶縁酸化膜、４０９・・
・・・・絶縁チツ化膜、４１０・・・・・・絶縁酸化族
・
第１ 旧
」ｒし２て凹（ｂ）
め３制（ｆ）FIG. 1 is a structural sectional view of a conventional semiconductor device. 101...P type substrate, 102...N+
Embedded layer. 103...Nm epitaxial layer, 104...
...P type separation layer, 105...P type V) NP
N) Emitter and collector of transistor space and injector, 106... NPN) Emitter and collector of transistor, 107... Electrode, 108...
. . . Insulating film. FIGS. 2A to 2F are cross-sectional views of the manufacturing process showing another conventional example. 201...P-type substrate, 202...N
Mold buried layer, 203,...Nfi epitaxial layer,
204... Insulating oxide film, 205... Insulating silicon film, 206... Insulating oxide group, 207...
...Opening, 20B...Insulating oxide group, 2
09... Insulating silicon film, 210... Insulating oxide film, 211... Polycrystalline silicon, 212
213... Insulating nitride film for insulation base, 214... P-type NPN) transistor active space region, 215...
・Boron-doped polycrystalline silicon, 216...P
Mold region, 217...Hydraulic doped polycrystalline silicon, 218...Aluminum electrode, 219...
. . . Insulating oxidation group. FIGS. 3(a) to 3(f) are process cross-sectional views showing the first embodiment of the present invention. 301...P type substrate, 302...N+
mold embedding layer. 303...Insulating oxide group, 304...Polycrystalline silicon, 305...Insulating oxide group, 306
...Insulating oxidation 1ll (,307...Opening, 308...Selective epitaxial layer, 30
9...Insulating acid dielectric film, 310...Insulating nitriding section, 311...P-type side diffusion layer, 312
...PfiNPN) transistor active base region. '313...H-doped polycrystalline silicon %
314...Aluminum electrode% 315...
N+ type NPN transistor emitter and collector region. FIGS. 4(a) to 4(e) are process cross-sectional views showing the second embodiment of the present invention. 401...P-type substrate, 402...N+
mold embedding layer. 403... Insulating oxide group, 404... Polycrystalline silicon, 405... Insulating oxide film, 406
...Opening m%407...Selected epitaxial layer, 408...Insulating oxide film, 409...
...Insulating silicon film, 410...Insulating oxide group, 1.
Claims (1)
を選択的に形成する工程と、前記半導体基板の一部を蕗
出させるような少なくとも一つの開口Ｓを設ける工程と
、前記開口部に単結晶半導体層を選択的に形成する工程
とを有し、前記単結晶半導体層内に素子領域を形成する
工程とを有することを特徴とする半導体装置の製造方法
。a step of selectively forming a polycrystalline semiconductor layer on one main surface of a semiconductor substrate via an insulating film; a step of providing at least one opening S for protruding a part of the semiconductor substrate; 1. A method of manufacturing a semiconductor device, comprising: selectively forming a single crystal semiconductor layer in the single crystal semiconductor layer; and forming an element region within the single crystal semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225815A JPS60117773A (en) | 1983-11-30 | 1983-11-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225815A JPS60117773A (en) | 1983-11-30 | 1983-11-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60117773A true JPS60117773A (en) | 1985-06-25 |
Family
ID=16835226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58225815A Pending JPS60117773A (en) | 1983-11-30 | 1983-11-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60117773A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01214166A (en) * | 1988-02-23 | 1989-08-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit device with bipolar transistor |
| JPH0246734A (en) * | 1988-08-08 | 1990-02-16 | Mitsubishi Electric Corp | Semiconductor integrated circuit device having bipolar transistor |
-
1983
- 1983-11-30 JP JP58225815A patent/JPS60117773A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01214166A (en) * | 1988-02-23 | 1989-08-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit device with bipolar transistor |
| JPH0246734A (en) * | 1988-08-08 | 1990-02-16 | Mitsubishi Electric Corp | Semiconductor integrated circuit device having bipolar transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4378630A (en) | Process for fabricating a high performance PNP and NPN structure | |
| EP0039411B1 (en) | Process for fabricating an integrated pnp and npn transistor structure | |
| JPH08306700A (en) | Semiconductor device and its manufacture | |
| JPS6148784B2 (en) | ||
| JP2629644B2 (en) | Method for manufacturing semiconductor device | |
| JPH05235017A (en) | Semiconductor device | |
| JPH0340938B2 (en) | ||
| JPS60117773A (en) | Manufacture of semiconductor device | |
| KR100580115B1 (en) | Self-aligned bipolar semiconductor device and manufacturing method of the same | |
| JPS59108325A (en) | Manufacture of semiconductor device | |
| JPH05283520A (en) | Manufacture of semiconductor device | |
| JPH0482180B2 (en) | ||
| JP2763105B2 (en) | Method for manufacturing semiconductor device | |
| JP3082800B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3361110B2 (en) | Method for fabricating a CMOS structure | |
| JPH07235547A (en) | Manufacture of semiconductor integrated circuit | |
| KR100275537B1 (en) | Method for fabricating bipolar transistor using over-growth of collector epitaxial layer | |
| JP2858510B2 (en) | Method for manufacturing semiconductor device | |
| JP2812282B2 (en) | Method for manufacturing semiconductor device | |
| JP3001340B2 (en) | Manufacturing method of bipolar integrated circuit | |
| KR930011542B1 (en) | Manufacturing method of bipolar transistor | |
| JP3209443B2 (en) | Manufacturing method of bipolar transistor | |
| KR910005393B1 (en) | Structure and manufacturing method of complex semiconductor element | |
| JP2892436B2 (en) | Method for manufacturing semiconductor device | |
| JPH11354530A (en) | Bi-polar type semiconductor device and its manufacture |