JPH0246734A - Semiconductor integrated circuit device having bipolar transistor - Google Patents

Abstract

PURPOSE:To realize reduced base-collector junction capacitance and to obtain reduced resistance value of base current by forming an insulating layer directly under an external base layer and providing a conductor for providing a base electrode in contact with the side wall of an active base region. CONSTITUTION:After a resist film 704 and a nitride film 301 on a polysilicon film 102 are removed, a P-type dopant and an N-type dopant are implanted sequentially into the polysilicon film 102 which is to serve as an emitter electrode lead-out layer. By annealing, an active base layer 7 and an emitter layer 9 are formed concurrently. Simultaneously therewith, an external base layer 8 is also obtained by diffusion of the P-type dopant from the polysilicon film 101 doped with the P-type dopant. Then, a PSG film 400 is deposited all over the surface and annealed to bake it. Contacts are formed at predetermined positions and an emitter electrode 600, a base electrode 601 and a collector electrode 602 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having bipolar transistors that are required to operate at high speed.

[Prior Art] FIGS. 2A to 2F are cross-sectional views showing the main manufacturing process steps of a bipolar transistor in a conventional method for manufacturing a semiconductor integrated circuit device.

Hereinafter, a conventional manufacturing method will be briefly explained with reference to the drawings.

After forming an n-type (n+ type) collector buried layer 2 with a high impurity concentration on a p-type (p-type) silicon substrate 1 with a low impurity concentration, an n-type (n-type) with a low impurity concentration is formed on the collector buried layer 2. Grow epitaxial layer 3. Next, the inter-element isolation groove 1
0 is formed to a depth that reaches the semiconductor substrate 1, and after forming the p-type layer 5 for channel cut, the groove 10 is filled with the isolation oxide film 4. Thereafter, the surface of the epitaxial layer 3 is exposed by etching back the entire surface, and after several polysilicon films 100 are formed on the entire surface, an oxide film, a nitride film, and an oxide film are sequentially deposited in this order to a predetermined thickness.

Next, patterning is performed using photolithography and selective etching techniques to form an oxide film 200 on the area that is to become the external base.
, a composite film consisting of a nitride film 300 and an oxide film 201 is formed (see FIG. 2A).

Next, using a resist film (not shown) as a mask, only the polysilicon film 100 in the area that will become the extraction layer of the collector electrode (the left side area of the isolation oxide film 4 on the right side in the figure) is removed. After removing the oxide film 201 on the upper layer of the composite film,
By performing selective oxidation using the nitride film 300 as a mask, the polysilicon film 100 is changed into oxide films 110 and 111, and a thick oxide 114112 is grown on the exposed surface of the epitaxial layer 3. Next, using these selective oxide films 110, 111, and 112 as masks, n-type impurity ions are implanted into the polysilicon film 101 under the nitride film 300 (see FIG. 2B).

A diffusion window is selectively opened in the oxide film 112 and a high concentration n-type impurity is diffused to form the collector electrode extraction layer 6. After the surface of the collector electrode extraction layer 6 is oxidized to form an oxide film 210, the oxide film 110 on the region to become the active base layer is removed by etching using the nitride film 300 as a mask. At this time, the oxide films 111, 112, and 210 are covered with a resist film (not shown) to prevent them from being etched, and the oxide film 110 is etched. After removing the resist film (not shown), the nitride film 300 on the polysilicon film 101 is removed. The oxide film 200 is removed. After that, an oxide film 202 is formed as a protective mask during ion implantation, and sintering is performed after implanting n-type impurities.
At the same time as the active base layer 7, an n-type impurity is diffused from the polysilicon film 102 containing the n-type impurity in the previous implantation to form the external base layer 8 (see FIG. 2C).

After depositing the oxide film 203 on the entire surface, only the oxide films 202 and 203 on the region to become the emitter are removed, a second polysilicon film 120 is formed, n-type impurity ions are implanted, and annealing is performed. The emitter layer 9 is formed by diffusing n-type impurities from the polysilicon film 120 containing n-type impurities.
to form.

Thereafter, a nitride film 301 is formed on the polysilicon film 120 (see FIG. 2D).

Next, the nitride film 301, the n+ polysilicon film 1201, and the oxide films 203 and 202 other than the emitter layer 9 are sequentially removed using the resist film as a mask, and then the resist film is removed. Furthermore, using the nitride film 301 as a mask, low-temperature oxidation (800~800
50° C.) to form a thick oxide film 220 on the side wall of the n+ polysilicon film 120 and a thin oxide film (not shown) on the surface of the p+ polysilicon 11!102. Thereafter, the thin oxide film (not shown) on the polysilicon film 102 is removed using the nitride film 301 as a mask, and the entire surface of the nitride film 301 is wet-removed (with phosphoric acid).
01 (see Figure 2E).

Thereafter, P S 0M400 is deposited, annealed and hardened, and contacts are formed to form emitter electrodes 600. A base electrode 601 and a collector electrode 602 are respectively formed (see FIG. 2F).

[Problem to be solved by the invention] Since the conventional semiconductor device is configured as described above,
The base-collector junction capacitance due to the inactive base region (external base) is large. This acts as a parasitic capacitance for the flow of base current, and the long conduction distance between the active base layer and the base electrode via the external base layer creates a large resistance to the base current, which reduces the high-speed operation of the transistor. It was the cause.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a semiconductor integrated circuit device having a bipolar transistor that reduces the junction capacitance between the base and the collector and also reduces the resistance value of the base current. With the goal.

[Means for Solving the Problems] A semiconductor integrated circuit device having a bipolar transistor according to the present invention includes a semiconductor substrate of a first conductivity type having a main surface, and a semiconductor integrated circuit device formed at a first depth from the main surface of the semiconductor substrate. a first semiconductor layer of a second conductivity type, a conductor buried within the first semiconductor layer at a second depth shallower than the first depth; a second semiconductor layer of the first conductivity type formed in contact with the sidewall of the conductor;
a third semiconductor layer of a second conductivity type formed within the semiconductor layer; a first conduction terminal connected to the first semiconductor layer;
A second conduction terminal connected to the conductor, a control terminal connected to the third semiconductor layer, a first insulating film formed on the lower surface area of the conductor, and the first conduction terminal are connected together. and a second insulating film formed on the side wall of the second semiconductor layer.

[Operations] In this invention, since the insulating layer is formed directly under the external base layer, the parasitic capacitance of the transistor is reduced, and the conductor that becomes the base electrode is in contact with the sidewall of the active base region, so the parasitic resistance is reduced. Ru.

[Embodiment] FIGS. 1A to 1G are cross-sectional views showing main process steps in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to the drawings.

First, after forming an n medium flexor buried layer 2 on a p-type silicon substrate 1, an inter-element isolation trench 10 reaching the silicon U plate 1 is formed. After forming a p-type layer 5 for channel cut by injecting p-type impurities into the bottom of the groove 10, the isolation oxide film 4 is filled in the groove 1°, and the upper surface of the collector buried layer 2 is exposed by etching back the entire surface. . After that, an oxide film 110 is formed on the collector buried layer 2. A polysilicon film 101 and an oxide film 111 are deposited in this order to a predetermined thickness (see FIG. 1A).

Thereafter, in order to open the active transistor region and the collector electrode extraction region, photolithography is used to open the oxide film 111, the polysilicon film 101, and the like using the resist film 700 as a mask. The oxide film 110 is sequentially removed using an anisotropic etching method to expose the collector buried layer 2. At this time, the polysilicon film 101 which becomes the external base extraction electrode is
The side is slightly etched to form an opening larger than the opening width of the oxide film 110 (see FIG. 1B).

After removing the resist film 700, n+ type epitaxial layers 3a and 3b are formed on the collector buried layer 2 as an active region and a collector electrode extraction region of the transistor. Incidentally, the epitaxial layers 3a and 3b are grown up to the upper surface of the polysilicon film 101 which becomes the external base extraction electrode. After that, the epitaxial layers 3a, 3
A polysilicon film 102.b is formed on the polysilicon film 102. A nitride film 301 is sequentially deposited. Next, an epitaxial layer 3b which will become an n-type collector region and a polysilicon film 1 which will become an external base extraction electrode.
01, a predetermined region of the resist film 700 is opened using photolithography. Using the opened resist film 701 as a mask, the exposed nitride film 301 on the polysilicon film 102 is removed (see FIG. 1C).

After removing the resist film 701, selective oxidation is performed using the nitride film 301 as a mask to oxidize the polysilicon films 101 and 102. This oxidation causes the oxide film 1
An oxide film 112 is formed which is integrated with the epitaxial layer 3b and the polysilicon film 1 which becomes the external base electrode.
An isolation oxide film 112 is formed between 01 and 01.

Next, using a resist film 703 with an opening only above the collector electrode extraction area by photolithography as a mask, the n-
The nitride film 301 above the epitaxial layer 3b is removed.

Furthermore, the polysilicon film 1 with the high concentration n-type impurity exposed
After injecting into 02, by sintering, n
A +-type collector electrode extraction layer 6 is formed (see FIG. 1D).

Subsequently, after removing the resist film 703, the nitride film 301 is removed.
By performing selective oxidation again using the mask as a mask, the polysilicon layer 102 on the flapper electrode extraction layer 6 is changed into an oxide film 121 having a predetermined depth.

Furthermore, in order to open above the external base electrode layer, a resist film 704 is formed by photolithography, and this is used as a mask to expose the exposed nitride film 301 and polysilicon film 102.
, and then remove the polysilicon film 1 directly below the oxide film 111.
High concentration n-type impurity ions are implanted into 01. In this implantation, since the sufficiently thick oxide film 121 serves as a mask for the ion implantation, the ions are not implanted into the collector electrode extraction layer 6 (see FIG. 1E).

Resist film 704, nitride film 3 on polysilicon film 102
After removing 01, an n-type impurity and an n-type impurity are sequentially implanted into the polysilicon film 102 which will become an emitter electrode extraction layer. When annealing is performed, impurities are diffused from the polysilicon film 102 containing p-type and n-type impurities into the n-epitaxial layer 3, and an active base layer 7 and an emitter layer 9 are simultaneously formed due to the difference in the degree of diffusion. be done.

At the same time, the external base layer 8 is formed by diffusion of n-type impurities from the polysilicon film 101 containing n-type impurities by the aforementioned implantation. Note that during this n-type impurity implantation, the polysilicon film 101 for taking out the external base electrode is
The upper oxide film 111 acts as a mask for ion implantation due to its thickness (see FIG. 1F).

Thereafter, the PSG film 400 is deposited on the entire surface and is annealed and baked. After that, contacts are formed at predetermined positions, and the emitter electrode 6001 base electrode 60
1 and collector electrode 602 (first
(See figure G).

Thereafter, steps such as forming a protective film on the upper surface continue, but since they are outside the scope of the present invention, their explanation will be omitted here.

In the above embodiments, bipolar transistors with specific conductivity types are described, but it goes without saying that bipolar transistors of opposite conductivity types can be similarly applied and produce similar effects.

[Effects of the Invention] As described above, according to the present invention, since the insulating layer is formed directly under the external base layer and the base electrode is taken from the sidewall of the active base region, parasitic capacitance and parasitic resistance are reduced. This has the effect of greatly contributing to the high-speed operation of the device.

[Brief explanation of the drawing]

1A to 1G are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS.
FIG. 2F is a cross-sectional view of main steps showing a conventional method for manufacturing a semiconductor integrated circuit device. In the figure, 1 is a silicon substrate, 2 is a collector buried layer, 3 is an epitaxial layer, 6 is a collector electrode extraction layer,
7 is an active base layer, 8 is an external base layer, 9 is an emitter layer, 101 is a polysilicon film, 110 is an insulating oxide film, 60
0 is an emitter electrode, 601 is a base electrode, and 602 is a collector electrode. In each figure, the same reference numerals indicate the same or corresponding parts. Figure 1A Figure 1C

Claims (1)

[Scope of Claims] A semiconductor substrate of a first conductivity type having a main surface; a first semiconductor layer of a second conductivity type formed at a first depth from the main surface of the semiconductor substrate; a conductor embedded in the semiconductor layer at a second depth shallower than the first depth; and a conductor formed in the first semiconductor layer and in contact with a sidewall of the conductor. a second semiconductor layer of a first conductivity type; and a third semiconductor layer of a second conductivity type formed within the second semiconductor layer.
a first conduction terminal connected to the first semiconductor layer, a second conduction terminal connected to the conductor, and a control terminal connected to the third semiconductor layer; a first insulating film formed on the lower surface region of the conductor; and a second insulating film formed on the sidewall of the second semiconductor layer on the side where the first conduction terminal is connected. A semiconductor integrated circuit device having a bipolar transistor, comprising: