JPS60107831A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lead out an electrode positively even in a small hole by burying the inside of an opening with a laminate consisting of polycrystalline Si and a Pt silicide layer and forming an Al wiring to the upper section of the opening when source-drain regions are diffused and shaped to the surface layer section of a semiconductor substrate, the whole surface is coated with an inter-layer insulating film, the opening is bored and electrodes are each formed to these regions. CONSTITUTION:A thick field insulating film 12 is formed to the peripheral section of a P type Si substrate 11, N<+> type source-drain regions 16 are diffused and shaped to the surface layer section of the substrate 11 surrounded by the insulating film 12, and a gate electrode 14 surrounded by an insulating film 15 is formed between these regions 16. The whole surface is coated with an inter-layer insulating film 17, contact holes 18 are bored made to correspond to the regions 16, and platinum silicide layers 19 are buried in the contact holes first. A polycrystalline Si layer 20 is grown on the whole surface, and annealed in an atmosphere at approximately 600 deg.C, Si atoms in the layer 20 are diffused in the direction of the substrate 11 through the layers 19, and Si layers 21 are grown under the layers 19. The unnecessary layer 20 remaining on the film 17 is removed through etching, and Al wirings 22 are applied on the layers 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and is used in an LSI having a small trflC contact hole.

[Technical background of the invention]

FIG. 1 shows a conventional n-channel MO8 type semiconductor device.

According to this, a polycrystalline silicon gate electrode surrounded by a thick oxide film for isolation between elements and an insulating film 5 is provided on the upper surface of a p-type silicon substrate l, and the silicon Near the upper surface of the substrate l, source and drain regions 6, which are n-diffusion tops, are formed, and the insulating film interposed between the gate electrode and the substrate l is a gate oxide film J.

An interlayer insulating film 7 is formed on all of these, and an opening g is provided for contacting the source and drain regions, and electrode wiring 9 formed by aluminum evaporation is provided.

[Problems with background technology]

However, the deposition thickness of vapor-deposited aluminum in such openings is not uniform.
), compared to the thickness a of the aluminum layer t on the insulating film around the opening g, the thickness b at the inner frame of the opening is
When the opening has a square shape with a side of 5 μm, the thickness is only about jtO%. This is because the step part of the insulating film becomes a shadow during vapor deposition, so if the opening becomes even smaller, the thickness of the aluminum vapor deposited on the insulating film and inside the opening will be significantly reduced, as shown in Figure 2 (b). This may cause a difference in step strength and worsen the step force, and may cause a discontinuous portion of the deposited film in the middle of the opening wall. The occurrence of such discontinuities causes problems such as poor or incomplete connections between the source and drain regions and the wiring, leading to decreased reliability and product defects due to potions, disconnections due to large currents, and the like.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device in which electrodes can be drawn out reliably even in small contact holes.

[Summary of the invention]

To achieve the above object, a semiconductor device according to the present invention includes a contact hole opened in an interlayer insulating film formed on a silicon substrate, a silicon common-mode diffusion layer formed on the silicon substrate in the contact hole, It has a metal silicide layer as an upper layer, and an aluminum wiring layer formed on the metal silicide layer, which causes connection failures that tend to occur in small contact holes in conventional high-density semiconductor devices. can be prevented.

Further, in the semiconductor device manufacturing method according to the present invention for realizing such a semiconductor device, there are a step of forming a contact hole by making an opening in an interlayer insulating film formed on a silicon substrate, and a step of forming a contact hole on the entire surface of a metal film. a step of annealing in a predetermined heating atmosphere to form a metal silicide layer; a step of removing the metal film remaining on the interlayer insulation crotch; and forming a polycrystalline silicon layer on the entire surface. a step of annealing in a predetermined heating atmosphere to form a silicon growth layer by in-phase diffusion of silicon; a step of removing the polycrystalline silicon layer remaining on the interlayer insulation crotch by etching; and a step of etching the contact. Embodiments of the Invention First, we will explain the in-phase growth phenomenon of silicon, which is the basic principle of the present invention. explain.

this is/? 1975 Journal of the American Society of Applied Physics (J.

This is a phenomenon reported in a paper by Kana IJ (0anali) and others published in A, P, VOl, 4'l CogJ Page), in which a layer of a metal silicide, such as platinum silicide, is deposited on a silicon substrate. When a polycrystalline silicon layer is formed on top and annealed in a boo'c atmosphere, the silicon substrate in the polycrystalline silicon undergoes solid phase diffusion through the platinum silicide layer, forming a solid phase growth layer of silicon on the silicon substrate. This is a phenomenon that can be obtained. At this time, the platinum silicide layer moves upward as the silicon layer grows and is finally replaced by the polycrystalline silicon layer.Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a cross-sectional view showing each step of forming a contact hole and its lead-out portion in the method for manufacturing a semiconductor device according to the present invention, and FIG. The completed state is shown. In this completed n-channel MO8 semiconductor device, an interlayer insulating film 17 is formed on the source and drain heads /L formed on the surface side of the p-type silicon substrate /L.
A contact hole /g is provided in a part of the source/drain head /6 for drawing out the source and drain, and in this contact hole 1g there is a silicon solid phase growth layer 21 on the silicon substrate 11 and a silicon solid phase growth layer 21 on the silicon substrate 11. A metal silicide layer /9 is formed on the metal silicide layer, and an aluminum wiring layer 22 is further formed on this metal silicide layer.

Next, the process of manufacturing a semiconductor device having such a configuration is described in 11.
Follow the staff and explain.

FIG. 3(a) shows a floating gate type n-channel MO8 semiconductor device with a contact hole opened, and the numbers // to /g are the numbers /-II in the conventional example in FIG.
and is manufactured using normal MO8 manufacturing techniques.

In this state, approximately 1000 A of platinum is deposited on the entire surface by vapor deposition, sputtering, etc., and annealing is performed in an atmosphere of approximately 100 C for approximately 7 hours, resulting in contact with the n+ region of the silicon substrate. The platinum layer is grown as a platinum silicide layer/9. When the platinum layer remaining on the interlayer insulating film other than the contact hole is removed using aqua regia, the state shown in Figure 3 φ) is obtained.Next, the polycrystalline silicon layer is coated to a total thickness of about 5000 A. It is formed by the CVD method (Figure 14 J (C)).

When annealing is performed in this state for about 2 hours in an atmosphere of about 6θθ°C, the silicon atoms in the polycrystalline silicon J diffuse into the silicon substrate through the silicide white -f, Psiq due to solid state diffusion phenomenon. Therefore, a silicon growth layer 2/ is formed on the silicon substrate ll, and a silicon silicide layer 2/ is formed on the silicon substrate ll.
9 moves upward as the silicon growth layer 21 grows (FIG. 3(d)).

After that, the polycrystalline silicon layer remaining on the interlayer insulating film/7 is removed by plasma elastane using defluorinated methane (CF4), and an aluminum wiring layer is formed, as shown in Fig. 3 (θ). It will be in a completed state.

In the above steps, the upper surface of the white silicide layer /q on the silicon growth layer 2/ is flush with the upper surface of the interlayer R film 17 to facilitate the formation of the aluminum wiring.

In the above embodiments, platinum silicide was used as the metal silicide necessary for solid-phase growth of silicon, but in addition to platinum, palladium (PCl) and chromium (Or) were used as metal silicides.
, nickel (IJi) 4F may be used, and amorphous silicon may be used instead of polycrystalline silicon).

Further, in the embodiment, an n-channel MO8 type semiconductor device has been described, but the present invention can be similarly applied to a p-channel MOBm semiconductor device.

〔Effect of the invention〕

In the semiconductor device according to the present invention as described above, the inside of the contact hole is filled with a silicon solid-phase growth layer and a metal silicide layer formed thereon, so even if the contact hole is small, aluminum wiring can be formed. During the evaporation process, the stepped portion of the interlayer insulation film does not become a shadow, and highly reliable electric conductor extraction without discontinuities can be performed. This is particularly important for the upper surface of the metal silicide layer or the interlayer insulation 1! Particularly good results can be obtained if the upper surfaces of e, .

Further, the method for manufacturing a semiconductor device according to the present invention makes it possible to stably manufacture the semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the configuration of a conventional MO8 semiconductor device,
FIG. 2 is a diagram showing problem 7 when a contact hole is small and out of place in a conventional semiconductor device, and FIG. 3 is a cross-sectional view for each f degree showing a semiconductor device and its manufacturing method according to the present invention. /, //... silicon substrate, 2. /2・
... Thick) Oxide film, 3, /3... Gate oxide film, Hiroshi,
/4'...Gate electrode, S. 15... Insulating film, 6, 16... Source, drain overhead, t. 17... Le 1 insulating film, g, 1g... Contact hole, 22... Electrode wiring, /? ...Platinum silicide layer, Uθ...polycrystalline 71137 layer, Nido silicon solid phase growth layer. Applicant's agent Seitaku Inomata 1 Kuchi (b) b2 Kasumi 6 (e) et al. 3 Figure

Claims (1)

[Claims] 1. A contact hole opened in an interlayer insulating film formed on a silicon substrate, a silicon in-phase growth layer formed on the silicon substrate in the contact hole, and a silicon in-phase growth layer formed on the silicon substrate. A semiconductor device comprising: a metal silicide layer; and an aluminum wiring layer formed on the metal silicide layer, wherein the top surface of the metal silicide layer substantially coincides with the top surface of the interlayer insulating film. A semiconductor device according to claim 7, characterized in that: J. The semiconductor device according to claim 1, wherein the metal silicide is platinum silicide. V. A process of forming an opening in an interlayer insulating film formed on a silicon substrate to form a contact hole, a process of forming a metal film on the entire surface, and annealing in a predetermined heating atmosphere to form a metal silicide layer. a step of removing the metal film remaining on the glabella insulating film; a step of forming a polycrystalline silicon layer on the entire surface; and annealing in a predetermined heating atmosphere to achieve solid phase diffusion of silicon. forming a silicon solid-phase growth layer by etching away the polycrystalline silicon layer remaining on the interlayer insulating I film, and etching the metal silicide layer formed in the contact hole. A method for manufacturing a semiconductor device, comprising the steps of: forming a contacting wiring layer.