JPS60106173A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60106173A JPS60106173A JP21450183A JP21450183A JPS60106173A JP S60106173 A JPS60106173 A JP S60106173A JP 21450183 A JP21450183 A JP 21450183A JP 21450183 A JP21450183 A JP 21450183A JP S60106173 A JPS60106173 A JP S60106173A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- gate
- polycrystalline silicon
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000010354 integration Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000011282 treatment Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置の製造方法、詳しくはＭＯＳトラン
ジスタ等の製造において耐圧性に優れたデー１−酸化膜
を形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a D1-oxide film having excellent voltage resistance in the manufacture of MOS transistors and the like.
（２）技術の背景
従来のＭＯＳ ｌ−ランジスタの製造工程においては、
例えばｐ型シリコン基板に選択酸化法によってフィール
ド酸化１挨を作り、そのときに用いた窒化膜を全面エツ
チングにより除去し、ゲート酸化法によりゲート作成領
域（シリコン基板の露出した部分）を酸化してゲート酸
化膜を作る工程が含まれる。(2) Background of the technology In the conventional manufacturing process of MOS l-transistor,
For example, a field oxide film is formed on a p-type silicon substrate by selective oxidation, the nitride film used at that time is removed by etching the entire surface, and the gate forming area (exposed part of the silicon substrate) is oxidized by gate oxidation. This includes the process of creating a gate oxide film.
（３）従来技術と問題点
最近の半導体集積回路の高集積化の要求に答えるべく、
不純物拡散領域は浅く、またゲート酸化膜は薄く形成さ
れる傾向にあり、薄い酸化膜の耐圧性が問題となり、耐
圧が向上せしめられたゲート酸化膜の製造方法がめられ
ている。(3) Prior art and problems In order to meet the recent demands for higher integration of semiconductor integrated circuits,
Impurity diffusion regions tend to be shallow and gate oxide films tend to be formed thinly, and the voltage resistance of thin oxide films becomes a problem, and a method of manufacturing a gate oxide film with improved voltage resistance is sought.
ところで従来の酸化膜の製造においては、基板シリコン
が機械的研摩や薬品処理を受けるため熱酸化で生成する
酸化膜にピンホールの如き欠陥を生じ、その結果酸化膜
の耐圧の向上が得られない欠点があった。However, in conventional oxide film manufacturing, the silicon substrate is subjected to mechanical polishing and chemical treatment, which causes defects such as pinholes in the oxide film generated by thermal oxidation, and as a result, the withstand voltage of the oxide film cannot be improved. There were drawbacks.
（４）発明の目的
本発明は上記従来の欠点に鑑み、半導体集積回路の高集
積化に対応することのできる薄いゲート酸化膜を、その
耐圧を向」二せしめる如くに！Ｉ！！Ｉ造する方法を提
供することを目的とするものである。(4) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides a thin gate oxide film that can cope with higher integration of semiconductor integrated circuits, and improves its breakdown voltage! I! ! The purpose of this invention is to provide a method for manufacturing.
（５）発明の構成
そしてこの目的は本発明によれは、シリコン部、（、板
にフィールド酸化膜を選択的に形成し、前記フィールド
酸化＋１Ｑ形成に用いたマスクを１；１ミ去し仝而にシ
リコンをコニピタキシャル成長する一＋ｘ 、＋’ｌ！
、曲ｌ、己エピタキシャル成長により作られたシリニＩ
ンＩ・、ｖｉ ｊ、、而を酸化し２−（チー１酸化化股
を作る〕こめの１′１（化）悦を作り、仝而に多結晶シ
リコン膜を被層する−１−イ”１）、ｌ１ｉｉ記多結晶
シリ′：ｌンｊ模を選択的にエツチングし゛Ｃゲー１へ
電極を作り、このゲート電極をマスクにして１）１１記
酸化脱のグー１−酸化脱以外の部分をエツチングする工
程を含むことを特徴とする半導体装置の製造方法を提供
することによっ−（達成される。(5) Structure and object of the invention According to the present invention, a field oxide film is selectively formed on a silicon portion (and a plate), and the mask used for forming the field oxidation +1Q is removed by 1 mm. And growing silicon conipitaxially +x, +'l!
, song I, Sirini I made by self-epitaxial growth
oxidize the 2-(chii 1 oxidized portion) to form 1'1(oxide), and cover it with a polycrystalline silicon film.-1-i. ``1) Selectively etching the polycrystalline silicon 1'' described in 11ii to form an electrode on the C gate 1, and using this gate electrode as a mask 1) 11. This is achieved by providing a method for manufacturing a semiconductor device characterized by including a step of etching a portion.
（６）発明の実施例 以下本発明実施例を図面によっ°ζ詳説する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明者は単結晶シリコンをエピタキシャル成長しそれ
を酸化すると、ピンホール等の欠陥のない良好な酸化膜
か得られることを実験によって僅かめた。その理由は、
エピタキシャル成長した単結晶シリコンは、化学気相成
長法で作られ、機械的（１１１摩や薬品処理にさらされ
ることかないからであると解される。本発明はかかる現
象を利用するもの−Ｃある。The present inventor has experimentally determined that by epitaxially growing single crystal silicon and oxidizing it, a good oxide film without defects such as pinholes can be obtained. The reason is,
This is understood to be because epitaxially grown single crystal silicon is produced by chemical vapor deposition and is not exposed to mechanical polishing or chemical treatments.The present invention utilizes such phenomena.
第１図以下に本発明の方法を実施する工程におりる半導
体装置間１；Ｉｉか断面図で小される。先ず第１図にボ
される如く、フィールＩ・ｊｌＱ化法によってシリコン
基］及】にフィール１−酸化膜２を形成し、仝面コーノ
チングによってソイールト酸化に用いた窒化１１Ｑ （
Ｓｉ、＋ Ｎ、ＩＩＩＱ、図示’ｕ’ −Ｕ’ ） 金
除去し、全面ニシリコンを１列えば１０００人の厚さに
エピタキシャル成長すると、ソリコン基板の露出した表
面上には小結晶シリコンＭ３ａか、またフィールド酸化
膜の上には多結晶シリコン屓（ポリシリコン層）３６か
成長する。1 and below are cross-sectional views of a semiconductor device 1; Ii undergoing a process of carrying out the method of the present invention. First, as shown in FIG. 1, a field 1-oxide film 2 is formed on the silicon base and the silicon base by the field I-jlQ method, and the nitride 11Q used for soil oxidation is formed by surface cornering.
(Si, +N, IIIQ, shown 'u' - U') After removing the gold and epitaxially growing full-surface di-silicon to a thickness of 1,000 wafers in one row, small crystal silicon M3a or A polycrystalline silicon layer 36 is grown on the field oxide film.
次いで第２図に示される如くゲーＩ−酸化法によって単
結晶シリコン層３ａの表面を酸化しケート酸化膜を作る
ための酸化ｎ？Ａ４を作る。酸化膜４は５００人程度の
膜厚にしたが、そのためには５００人の約半分の２５０
人の単結晶シリコンが酸化され（食われ） 、７５０人
程度の単結晶シリコンはそのまま残る。第２図に単結晶
シリコン部分３ａは白地で、また酸化した部分４は斜線
を付して示す。なおこのようにして単結晶シリコンを残
すとｉｉＪ圧性に優れた酸化膜が得られることか確認さ
れている。Next, as shown in FIG. 2, the surface of the single crystal silicon layer 3a is oxidized by the GaI oxidation method to form a gate oxide film. Make A4. The oxide film 4 was made to have a thickness of about 500 mm.
The human single crystal silicon will be oxidized (eaten away), and around 750 people's single crystal silicon will remain intact. In FIG. 2, the single crystal silicon portion 3a is shown in white, and the oxidized portion 4 is shown with diagonal lines. It has been confirmed that if monocrystalline silicon is left in this manner, an oxide film with excellent iiJ pressure properties can be obtained.
次いでゲートの下の不純物濃度を制ｆ１］ｌｌするだめ
のチャネルドーズとして例えばホｌコン（１３”）をイ
オン注入法で注入する。イオン注入のエネルギー、ドー
ズ量は形成されるべき素子の１１．ｌｊ性に対応して適
宜設定−する。Next, as a channel dose to control the impurity concentration under the gate, for example, Holon (13") is implanted by ion implantation. The energy and dose of ion implantation are determined according to the 11. Set as appropriate depending on the lj property.
引続き全面にポリシリコンを成長しポリシリコン膜５を
作る。ポリシリコン膜５は他の部分では配線として用い
られるから、その膜厚は配線の抵抗とゲート電極との関
係で適宜設定する。Subsequently, polysilicon is grown on the entire surface to form a polysilicon film 5. Since the polysilicon film 5 is used as a wiring in other parts, its film thickness is appropriately set depending on the relationship between the resistance of the wiring and the gate electrode.
次に全面にレジスト膜（図示せず）を塗布形成し、それ
をバターニングして得られるマスクをマスクにしてポリ
シリコン膜５をエツチングしてゲート電極５ａを作る。Next, a resist film (not shown) is applied and formed on the entire surface, and the polysilicon film 5 is etched using the mask obtained by patterning the resist film to form the gate electrode 5a.
引続きゲート電極５ａをマスクにしてケート酸化膜以外
の酸化膜をエツチング除去し、不純物拡ｆｉ＆によって
ソース６、ドレイン７を作る（第３図）。以下通常の工
程でＭＯＳトランジスタを作る。Subsequently, using the gate electrode 5a as a mask, the oxide film other than the gate oxide film is removed by etching, and a source 6 and a drain 7 are formed by impurity diffusion (FIG. 3). A MOS transistor is manufactured using the following standard steps.
上記から理解されうる如（、本発明の方法において酸化
膜４の形成において基板シリコンは機械的ｕＦ １４Ｊ
や薬品処理は全く行われないのでピンボールの如き欠陥
の少ない耐圧に優れた酸化膜が得られる。As can be understood from the above (in the method of the present invention, the substrate silicon is mechanically heated with uF 14J)
Since no chemical treatment is performed, an oxide film with excellent breakdown voltage and fewer defects such as pinballs can be obtained.
（、：発明の効果
以上詳細に説明した如く本発明によれば、薄い膜厚の耐
圧性に優れ欠陥の少ない酸化膜が得られるので、半導体
集積回路の高集積化と信頼性向上に効果大である。(,: Effects of the Invention As explained in detail above, according to the present invention, a thin oxide film with excellent voltage resistance and few defects can be obtained, which is highly effective in increasing the integration density and reliability of semiconductor integrated circuits. It is.
第１図ないし第３図は本発明の方法を実施する工程にお
けるゲート酸化膜部分の断面図である。
１−・シリコンＭ板、２− フィールド酸化膜、３ａ−
・−単結晶シリコン層、３ｂ・−ポリシリコン層、４−
酸化ｊ挨（５ｉＯｚ膜）、５−ポリシリコン膜、６−ソ
ース、７− ドレイン
第１図
第２図
第３図1 to 3 are cross-sectional views of the gate oxide film portion in the process of carrying out the method of the present invention. 1- Silicon M plate, 2- Field oxide film, 3a-
・-Single crystal silicon layer, 3b・-Polysilicon layer, 4-
Oxidized dust (5iOz film), 5-polysilicon film, 6-source, 7-drain Fig. 1 Fig. 2 Fig. 3
Claims (1)
記フィールド酸化膜形成に用いたマスクを除去し全面に
シリコンをエピタキシャル成長する工程、前記エピタキ
シャル成長により作られたシリコン層表面を酸化してゲ
ート酸化膜を作るだめの酸化膜を作り、全面に多結晶シ
リコンＩＩＱを被着する工程、前記多結晶シリコン膜を
選択的にエツチングしてゲート電極を作り、このゲート
電極をマスクにして前記酸化膜のゲート酸化膜以外の部
分をエツチングする工程を含むことを特徴とする半導体
装置の製造方法。selectively forming a field oxide film on a silicon substrate, removing the mask used for forming the field oxide film, and epitaxially growing silicon on the entire surface; oxidizing the surface of the silicon layer formed by the epitaxial growth to form a gate oxide film; A process of forming a final oxide film and depositing polycrystalline silicon IIQ on the entire surface, selectively etching the polycrystalline silicon film to form a gate electrode, and using this gate electrode as a mask, perform gate oxidation of the oxide film. A method for manufacturing a semiconductor device, comprising a step of etching a portion other than a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21450183A JPS60106173A (en) | 1983-11-15 | 1983-11-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21450183A JPS60106173A (en) | 1983-11-15 | 1983-11-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60106173A true JPS60106173A (en) | 1985-06-11 |
Family
ID=16656754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21450183A Pending JPS60106173A (en) | 1983-11-15 | 1983-11-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60106173A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5190584A (en) * | 1975-02-07 | 1976-08-09 | Handotaisochino seizohoho |
-
1983
- 1983-11-15 JP JP21450183A patent/JPS60106173A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5190584A (en) * | 1975-02-07 | 1976-08-09 | Handotaisochino seizohoho |
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