JPS60105277A - Manufacture of mos transistor - Google Patents
Manufacture of mos transistorInfo
- Publication number
- JPS60105277A JPS60105277A JP21205083A JP21205083A JPS60105277A JP S60105277 A JPS60105277 A JP S60105277A JP 21205083 A JP21205083 A JP 21205083A JP 21205083 A JP21205083 A JP 21205083A JP S60105277 A JPS60105277 A JP S60105277A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- oxide film
- doped
- conductive type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000012298 atmosphere Substances 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 239000007789 gas Substances 0.000 abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- KYKAJFCTULSVSH-UHFFFAOYSA-N chloro(fluoro)methane Chemical compound F[C]Cl KYKAJFCTULSVSH-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明Ｈｐポケットを有するＬ Ｄ Ｄ （Ｌｉｇｈｔ
ｙＤｏｐｅｃｌ Ｄｒａｉｎ ） トランジスタの製造
方法に関する。[Detailed description of the invention] [Technical field of the invention] LDD (Light) having a Hp pocket of the present invention
yDopecl Drain) relates to a method of manufacturing a transistor.
〔発明の技術的背景およびその問題点〕通常のＭＯＳ）
ランジスタは第１図に示すようにＰ型シリコン基板ｌ上
にゲート酸化膜２を形成し、イオン注入によりチャンネ
ル領域８を設けた後グー１［４ｉ１ｉｉ、４に対してセ
ルファラインでヒ素（八〇）をイオン注入しＮ十型ドレ
イン領域５１、Ｎ＋＋ソース領域５２を形成して製造さ
れている。しかしこのような構造のＭＯＳトランジスタ
では、１型ドレイン領域５１近傍に電界が集中し、正孔
−電子対が発生するため基板電流が増大し電子がゲート
電極４に注入される等の現象を生じ、動作安定性に問題
があった。これに対して第２図に示すようにゲート酸化
膜２の近傍にＮ型ドレイン領域６１とＮ型ソーヌ領域６
２を印加し、ドレイン領域６１近傍での電界集中を緩和
するＬ Ｄ Ｄ （ＬｉｇｈｔｙＤｏｄｅｄ Ｄｒａｉ
ｎ ） ｌＩｔ造のトランジスタが注目されている。し
かしながら、とのＬＤＤ トランジスタにおいても高濃
度、チャンネル領域が存在するため、バックゲートバイ
アス効果により、しきい値ｖｔｈの増大をもたらす欠点
がある。この欠点を克服するものとして、第８図に示す
ようなＮ型ドＶイン領域伍とＮ型ソーヌ領域６２の下に
Ｐ型領域ｎ。[Technical background of the invention and its problems] Ordinary MOS)
As shown in FIG. 1, the transistor is manufactured by forming a gate oxide film 2 on a P-type silicon substrate l, and forming a channel region 8 by ion implantation. ) is ion-implanted to form an N0-type drain region 51 and an N++ source region 52. However, in a MOS transistor having such a structure, an electric field concentrates near the type 1 drain region 51 and hole-electron pairs are generated, resulting in phenomena such as an increase in substrate current and injection of electrons into the gate electrode 4. , there were problems with operational stability. On the other hand, as shown in FIG.
2 is applied to relieve the electric field concentration near the drain region 61.
n) It-based transistors are attracting attention. However, since a highly doped channel region exists in the LDD transistor as well, there is a drawback that the threshold value vth increases due to the back gate bias effect. To overcome this drawback, a P-type region n is provided below the N-type doV-in region 5 and the N-type Saone region 62 as shown in FIG.
７２を形成するＰポケットつきのＬＤＤ構造のトランジ
スタが提案されている。このＰポケットＬＤＤトランジ
スタは、ショート羊ヤンネル効果抑ｆｆ＋ｌＪのだめの
高エネルギイオン注入が不要となるため、バックゲート
バイアス効果によるしきい値ｖｔｈの増大を考慮する必
要がなくなる。A transistor having an LDD structure with a P pocket forming a transistor 72 has been proposed. This P-pocket LDD transistor does not require high-energy ion implantation to suppress the short Jannell effect ff+lJ, so there is no need to consider an increase in the threshold voltage vth due to the back gate bias effect.
しかしながらこのような構造のＭＯＳ）ランジスタを製
造するためには、Ｎ型領域、Ｐ型領域、Ｎ＋型領領域形
成するため、８回のイオン注入が必要であり、プロセス
が複雑となる問題があった。However, in order to manufacture a MOS transistor with this structure, eight ion implantations are required to form an N-type region, a P-type region, and an N+-type region, which poses the problem of complicating the process. Ta.
本発明は上記事情を考慮してなされたもので、１回の不
純物拡散でＰポケットＬＤＤトランジスタを製造するこ
とができる、半導体装置の製造方法を提供することを目
的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture a P-pocket LDD transistor by one-time impurity diffusion.
この目的を達成するために本発明によるＭＯＳトランジ
スタの製造方法は、第１導電型半導体基板上に酸化膜を
介してゲート電極を形成する工程と、前記第１導電型半
導体基板上に第１導屯型を提供する第１の不純物と嬉２
導厩型を提供する第２の不純物とをドープしたドープト
酸化膜を形成する工程と、このドープト酸化膜上であっ
てポケット部となるべき領域上にのみ窒化膜を形成する
工程と、酸素雰囲気中にて熱処理する工程とを有するこ
と′ｆｆ：％歌とする。In order to achieve this object, the method for manufacturing a MOS transistor according to the present invention includes the steps of forming a gate electrode on a first conductive type semiconductor substrate via an oxide film, and forming a first conductive type semiconductor substrate on the first conductive type semiconductor substrate. The first impurity and happiness 2 that provide the shape
A step of forming a doped oxide film doped with a second impurity that provides a conductive type, a step of forming a nitride film only on the region that is to become a pocket portion on this doped oxide film, and a step of forming an oxygen atmosphere. and a step of heat treatment inside.
実施例の説明の前に本発明の原理を第４図、第５図を用
いて説明する。本発明は拡散するとＮ型となる不純物の
ヒ素（Ａθ）が酸素雰囲気中で拡散が促進され、Ｐ型と
なる不純物のホウ素（Ｊ３）が窒素雰囲気中で拡散が促
進されることを利用したものである。第４図に示すよう
に比抵抗ρ＝ｌＯ〜２ｏΩ口のＰ−型シリコン基板８の
土建、ヒ素をＬＯ２１Ｃｍ −”ホウ素をｔｏ ｍ の
濃度でドープした厚さ０．８μｍの酸化膜９を堆積する
。次に左半分に窒化膜１ｏを形成した後、酸素雰囲気中
で１０００ｔｌ’、３ｏ分１１」の拡散をおこなう。窒
化ｉｔｏがない右手分の領域では酸素雰囲気中で拡散が
おこなわれるが、左半分の領域では窒化膜１ｏがあるた
めに酸素雰囲気中でなく窒素雰囲気中で拡散がおこなわ
れることと等価となる。Before explaining the embodiments, the principle of the present invention will be explained using FIGS. 4 and 5. The present invention utilizes the fact that arsenic (Aθ), an impurity that becomes N-type when diffused, is promoted to diffuse in an oxygen atmosphere, and boron (J3), an impurity that becomes P-type, is promoted to diffuse in a nitrogen atmosphere. It is. As shown in FIG. 4, a P-type silicon substrate 8 with a specific resistance ρ = 10 to 20Ω is constructed, and an oxide film 9 doped with arsenic at a concentration of LO21Cm-" and boron tom with a thickness of 0.8 μm is deposited. Next, after forming a nitride film 1o on the left half, diffusion of 1000 tl', 3o/11'' is performed in an oxygen atmosphere. In the right-hand region where there is no ito nitride, diffusion takes place in an oxygen atmosphere, but in the left-hand half region, since there is a nitride film 1o, this is equivalent to diffusion taking place in a nitrogen atmosphere instead of an oxygen atmosphere.
したがって右半分の領域では第５ｔｇｌ（ｂ）に示すよ
うにヒ素（八〇）の拡散が促進され、シート抵抗ρＢ−
３０Ω／口、接合深さＸｊ＝０．４μｍのＮ十型領域１
１が形成される。これに対し左半分の領域では第５図（
ａ）に示すように、ホウ素（Ｂ）の拡散がより促進され
深さ０．１５μｍ 付近でヒ：４ｉ （Ａ ｓ ）の不
純物濃度と逆転するようになり、シート抵抗ρＢ−８０
０Ω／口、接合深さｘｊ＝０．１５４ｍのＮ型領域１３
と、シート抵抗ρｓ ＝ ２ ＫΩ／口、接合深さｘｊ
−〇、４μｍのＰ型領域１２とが同時に形成される。Therefore, in the right half region, the diffusion of arsenic (80) is promoted as shown in 5th tgl (b), and the sheet resistance ρB-
N-shaped region 1 with 30Ω/port and junction depth Xj=0.4μm
1 is formed. On the other hand, in the left half area, Figure 5 (
As shown in a), the diffusion of boron (B) is further promoted, and the impurity concentration becomes reversed to H:4i (A s ) near the depth of 0.15 μm, and the sheet resistance ρB-80
N-type region 13 with 0Ω/port and junction depth xj=0.154m
and sheet resistance ρs = 2 KΩ/mouth, junction depth xj
-〇, P-type region 12 of 4 μm is formed at the same time.
次に本発明の一実施例によるＭＯＳ）ランジスタの製造
方法全第６図を用いて説明する。まず比抵抗ＩＯ〜２０
Ω（７）のＰ−型シリコン基板１４に厚さ１．２μｍの
フィールド酸化膜１５を形成し、厚さ８００＾のゲート
酸化膜１６を形成する。次に製造されるＭＯＳ）ランジ
ヌタのしきい値ｖｔｈ制（イ）１のためホウ素（Ｂ）を
３０Ｋｅｖにて２ Ｘ ｔｏ” ｃＩｎ−”の公明でイ
オン注入する（第６図（ａ））。次にシート抵抗ρｅ＝
３００／口、厚さ０．４μｍの多結晶シリコン層１７を
堆積し、その上にＶジヌ）ｇ！Ｘ１８を形成する。しシ
スト膜１８をマヌクとして水素ガス（Ｈ２）と塩素カヌ
（Ｃ！１． ）または水素ガス（Ｈ２）とフロンガス（
ＯＦ４）とからなる反応性イオンガスにて多結晶シリコ
ン層１７、ゲート酸化＋Ｊｔ６を順次エツチングし、長
さ１．５μｍのグー）ＩＥｅ１７、ゲート１θ化膜１６
を形成する（第６図（ｂ））。次にレジヌト１ｌＫｔｓ
を除去した後ヒ素（Ａｓ）を１０２０ｍ−３、ホウ素（
Ｂ）を８−８
一８１Ｏドープした厚さ０．８μｍのドープトル化膜１
９をスパッタ法により堆積する。次にフッ化アンモニウ
ム（ＮＨ，Ｆ ）中に１０秒間浸し、上記ゲート酸化膜
１６、ゲート電極１７から々る２層構造の側壁に堆積し
ているドープトａ化嘆１９をとりさる。Next, a method for manufacturing a MOS transistor according to an embodiment of the present invention will be explained with reference to FIG. First, specific resistance IO ~ 20
A field oxide film 15 with a thickness of 1.2 μm is formed on a P-type silicon substrate 14 of Ω(7), and a gate oxide film 16 with a thickness of 800^ is formed. Next, in order to control the threshold voltage vth of the MOS (to be manufactured), the threshold voltage (a) of the MOS transistor is 1), boron (B) is ion-implanted at 30 Kev with a density of 2 x to "cIn-" (FIG. 6(a)). Next, sheet resistance ρe=
A polycrystalline silicon layer 17 with a thickness of 0.4 μm is deposited on top of the polycrystalline silicon layer 17. Form X18. The cyst film 18 is used as hydrogen gas (H2) and chlorine gas (C!1.) or hydrogen gas (H2) and chlorofluorocarbon gas (C!1.).
Polycrystalline silicon layer 17, gate oxidation + Jt6 are sequentially etched with reactive ion gas consisting of
(Fig. 6(b)). Next, Resinut 1lKts
After removing arsenic (As) and boron (
B) 8-8-81O doped film 1 with a thickness of 0.8 μm
9 is deposited by sputtering. Next, it is immersed in ammonium fluoride (NH,F 2 ) for 10 seconds to remove the doped a-oxide film 19 deposited on the sidewalls of the two-layer structure including the gate oxide film 16 and the gate electrode 17 .
平担部には厚さ０．２５μｍのドープト酸化膜１９が残
存している（第６図（Ｃ））。次にＬＰＯＶＤ（Ｌｏｗ
Ｐｒｅｓｓｕｒｅ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ
ＤｅｐｏＳｉｔｉｏｎ ）法にて厚さ０．２５μｍの窒
化膜２０を堆積する（第６図（ｄ））。次に水素ガス（
Ｈ２）とフロンガス（ＯＦ４） からなる反応性イオン
ガスにて平担部の窒化膜２０をエツチング除去し、２層
構造の側壁部にのみ窒化膜２０を残存させる・。本実施
例によればパターニングすることなく、Ｐポケット部を
形成する場所にのみ窒化ｒｉｇ ２０が残るように形成
できる利点がある。次に酸素雰囲気中にてｔｏｏ。A doped oxide film 19 with a thickness of 0.25 μm remains on the flat portion (FIG. 6(C)). Next, LPOVD (Low
Pressure Chemical Vapor
A nitride film 20 having a thickness of 0.25 μm is deposited by the DepoSition method (FIG. 6(d)). Next, hydrogen gas (
The nitride film 20 on the flat part is etched away using a reactive ion gas consisting of H2) and chlorofluorocarbon gas (OF4), leaving the nitride film 20 only on the sidewalls of the two-layer structure. According to this embodiment, there is an advantage that the nitrided rig 20 can be formed so as to remain only at the location where the P pocket portion is to be formed, without patterning. Next, in an oxygen atmosphere.
Ｃで３０分間熱処理し、シート抵抗ρ５＝３００／口、
接合深さｘｊ ＝ ０．４μｍのＮ十型ドレイン領域２
１１とＮ生型ンーヌ領域２１２、シート抵抗ρＳ−２に
Ω／口、接合深さＸｊ＝０゜４μｍのＰ型ポケット領域
２２１． ２２２、シート抵抗ρｓ ＝８００Ω／口、
接合深さｘｊ＝−０，１５μｍのＮ型ドレイン領域２８
１． Ｎ型ソーヌ領域２３２、全同時に形成する（第６
図（ｅ））。次に残存している窒化膜２０、ドープト酸
化＠１９を、水素ガス（Ｈ２）とフロンガス（ＯＦ４）
からなる反応性イオンガス にてエツチング除去する。Heat treated at C for 30 minutes, sheet resistance ρ5 = 300/mouth,
N-type drain region 2 with junction depth xj = 0.4 μm
11 and an N-type pocket region 212, a P-type pocket region 221 with a sheet resistance ρS-2 of Ω/mouth and a junction depth Xj=0°4 μm. 222, sheet resistance ρs = 800Ω/mouth,
N-type drain region 28 with junction depth xj = -0, 15 μm
1. N-type Saone regions 232 are formed all at the same time (sixth
Figure (e)). Next, the remaining nitride film 20 and doped oxide @19 are treated with hydrogen gas (H2) and fluorocarbon gas (OF4).
Remove by etching with reactive ion gas consisting of.
その後厚さ１．０μｍのｃｖＤ、；２化膜２４を堆積し
開口部を設ける。最後に４軍材料にてドＶイン電極２５
１、ソーヌ社極２５２を形成してＭＯＳ）ランジヌタが
完全する（第６図（ｆ））。Thereafter, a CVD film 24 having a thickness of 1.0 μm is deposited to form an opening. Finally, do V-in electrode 25 using the fourth material.
1. Form the Saunesha pole 252 to complete the MOS) lunge (FIG. 6(f)).
本実施例によれば、窒化１閘をパターニングすることな
くセルファラインで形成でき、かつ１回の拡散でＰ明領
域、Ｎ型領域、Ｎ＋製領領域形成が可能であり、大巾な
製造工程の簡略化が達成できる。According to this embodiment, one nitride layer can be formed by self-line without patterning, and a P-light region, an N-type region, and an N+ region can be formed by one diffusion, and the manufacturing process is wide-ranging. simplification can be achieved.
なお、先の実施例では窒化膜の形成をセルファラインで
形成したが、パターニングにより形成してもよい。この
ときは任意の形状でポケット部が形成できる。またエツ
チングするのに反応性イオンエツチング法を、堆積する
のにスパッタ法やＣＶＤ法を用いているが他の方法によ
りエツチングしたり、堆積したりしてもよい。Although the nitride film was formed by self-line in the previous embodiment, it may also be formed by patterning. At this time, the pocket portion can be formed in any shape. Although reactive ion etching is used for etching and sputtering or CVD is used for deposition, other methods may be used for etching or deposition.
以上の通り本発明によればＰ明領域とＮ型領域とＮ＋領
領域１妾の拡散で同時に形成することができ、大巾な工
程の簡略化が可能である。このような製造方法でつくら
れたＭＯＳ）ランジヌタはそのＬＤＤ構造のため、信頼
性が著しく向上し、バンクゲートバイアス１０Ｖでしき
い値ｖｔｈの増大（△ｖｔｈ ）をＩＶ以下に抑制する
ことが可能である。As described above, according to the present invention, the P-type region, the N-type region, and the N+ region 1 can be formed simultaneously by diffusion, and the process can be greatly simplified. Because of its LDD structure, the MOS (MOS) range nut manufactured using this manufacturing method has significantly improved reliability, and can suppress the increase in threshold value vth (△vth) to below IV with a bank gate bias of 10V. It is.
第１［ン１は通常のＭＯＳ）ランジヌタの断面図、第２
図はＬＤＤ構造のＭＯＳトランジスタの断面図、第８図
はＰボケツ）ＬｐＤｉ造のＭＯＳ）ランジヌタの断面図
、第４図、第５図（ａ）、 （ｂ）は本発明の詳細な説
明するための図、第６図（ａ）、 （ｂ）、 （（！Ｌ
（ｄ）、 （ｅ）、 （ｆ）は本発明の一実施例による
ＰポケットＬＤＤｍ造のＭＯＳ）ランジヌタの製造方法
を示す工穆図である。
１・・・Ｐ−型シリコン基板、２・・・ゲート酸化膜、
３・・・チャンネル領域、４・・・ゲート電極、５１・
・・Ｎ＋＋
型ドレイン領域、６２・・・Ｎ 型ソーヌ領域、６１・
・・Ｎ型ドレイン領域、６２・・・Ｎ型ソーヌ領域、７
１ 、７２・・・Ｐ型ポケット領域、８・・・Ｐ−型シ
リコン基板、９・・・ドープト酸化膜、ＩＯ・・・窒化
膜、１１・・・Ｎ＋＋拡散領域、１２・・・Ｐ型拡散領
域、１３・・・Ｎ型拡散領域、１４・・・Ｐ”％’２シ
リコン基板、１５・・・フィールド酸化膜、１６・・・
ゲート酸化膜、１７・・・多結晶シリコン層、１８・・
・レジスト膜、１９・・・ドープト酸化膜、２０・・・
窒化膜、２１１・・・Ｎ十型ドレイン領域、２１２・・
・Ｎ十型ソーヌ領域、２２１ 、２２２・・・Ｐ型ポケ
ット領域、２３１・・・Ｎ型ドレイン領域、２８２・・
・Ｎ型ソーヌ領域、Ｕ・・・ＣＶＤ酸化膜、２５１・・
・ドレイン電極、２５２・・・ソース電極。
出願人代理人 猪 股 清
第４図
ｎ
δ
第５図1st [N1 is a normal MOS] cross-sectional view of the lunge nut, 2nd
The figure is a cross-sectional view of a MOS transistor with an LDD structure, FIG. 8 is a cross-sectional view of a MOS transistor made of LpDi, and FIGS. 4, 5 (a), and (b) are detailed explanations of the present invention. Figure 6 (a), (b), ((!L
(d), (e), and (f) are schematic diagrams showing a method of manufacturing a P-pocket LDD (MOS) lunge according to an embodiment of the present invention. 1... P-type silicon substrate, 2... Gate oxide film,
3... Channel region, 4... Gate electrode, 51.
...N++ type drain region, 62...N type Saone region, 61.
...N-type drain region, 62...N-type Saone region, 7
1, 72...P type pocket region, 8...P- type silicon substrate, 9...doped oxide film, IO...nitride film, 11...N++ diffusion region, 12...P type Diffusion region, 13... N type diffusion region, 14... P''%'2 silicon substrate, 15... Field oxide film, 16...
Gate oxide film, 17... Polycrystalline silicon layer, 18...
・Resist film, 19... Doped oxide film, 20...
Nitride film, 211...N-type drain region, 212...
・N-type Saone region, 221, 222...P-type pocket region, 231...N-type drain region, 282...
・N-type Saone region, U...CVD oxide film, 251...
- Drain electrode, 252...source electrode. Applicant's agent Kiyoshi Inomata Figure 4 n δ Figure 5
Claims (1)
ート成極と、このゲート電極の両側の前記第１導電型半
導体基板上にそれぞれ形成された第２導電型のソース領
域およびドレイン領域と、前記ゲート電極下のチャネル
領域と前記ソース領域およびドレイン領域との間にそれ
ぞれ形成された、前記ソース領域およびドレイン領域よ
り不純物濃変の低い第２導電型の低濃度ソース領域およ
び低濃度ソース領域と、これら低濃度ソース領域および
低濃度ドレイン領域下にそれぞれ形成された第１導′屯
型不紬物領域とを有するＭＯＳ）ランジヌタの製造方法
において、 前記第１４電型半導体基板上に酸化膜を介してゲート電
極を形成する工程と、 前記第１導電型半導体基板上に第１導車型を提供する第
１の不純物と第２４電型を提供する第２の不純物とをド
ープしたドープト酸化膜を形成する工程と、 このドープト酸化１漠上であって、前記低濃度ソース領
域および低濃度ドレイン領域となるべき領域上にのみ窒
化嘆を形成する工程と、 酸素雰囲気中にて熱処理する工程と を有することを％微とするＭＯＳ トランジスタの製造
方法。[Claims] A gate electrode formed on a first conductive type semiconductor substrate via an oxide film, and a second conductive type formed on the first conductive type semiconductor substrate on both sides of the gate electrode. and a second conductivity type low concentration layer having a lower impurity concentration change than the source region and drain region, which are formed between a channel region under the gate electrode and the source region and the drain region, respectively. In the method for manufacturing a MOS transistor having a source region, a low concentration source region, and a first conductive type impregnated region formed under the low concentration source region and the low concentration drain region, the fourteenth electrode forming a gate electrode on the first conductive type semiconductor substrate via an oxide film; a first impurity providing a first conductive type and a second impurity providing a twenty-fourth conductive type on the first conductive type semiconductor substrate; a step of forming a doped oxide film doped with a doped oxide film; a step of forming a nitride film only on the doped oxide film and on regions to become the low concentration source region and the low concentration drain region; and an oxygen atmosphere. A method of manufacturing a MOS transistor, which includes a step of heat treatment inside.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21205083A JPS60105277A (en) | 1983-11-11 | 1983-11-11 | Manufacture of mos transistor |
| US06/670,010 US4597824A (en) | 1983-11-11 | 1984-11-09 | Method of producing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21205083A JPS60105277A (en) | 1983-11-11 | 1983-11-11 | Manufacture of mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60105277A true JPS60105277A (en) | 1985-06-10 |
Family
ID=16616032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21205083A Pending JPS60105277A (en) | 1983-11-11 | 1983-11-11 | Manufacture of mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60105277A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833594B2 (en) | 2001-01-23 | 2004-12-21 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit device and manufacture method therefore |
-
1983
- 1983-11-11 JP JP21205083A patent/JPS60105277A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833594B2 (en) | 2001-01-23 | 2004-12-21 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit device and manufacture method therefore |
| US7138311B2 (en) | 2001-01-23 | 2006-11-21 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit device and manufacture method therefore |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR920009745B1 (en) | Manufacturing method of semiconductor | |
| US4597824A (en) | Method of producing semiconductor device | |
| JPS61224459A (en) | Semiconductor device and manufacture thereof | |
| JPS60105277A (en) | Manufacture of mos transistor | |
| JP2985246B2 (en) | Method for manufacturing semiconductor device | |
| JPS61154172A (en) | Manufacture of semiconductor device | |
| KR100336572B1 (en) | Method for forming semiconductor device with gate electrode using poly silicon-germanium | |
| JP2581548B2 (en) | Method for manufacturing semiconductor device | |
| JP2808945B2 (en) | Method of manufacturing vertical MOS field effect transistor | |
| JPS6017965A (en) | Manufacture of semiconductor device | |
| JPS61295652A (en) | Manufacture of cmos-type semiconductor device | |
| JPH04283966A (en) | Manufacture of mos semiconductor device | |
| JPS6155965A (en) | Manufacture of nonvolatile semiconductor memory device | |
| JPH02103966A (en) | Manufacture of semiconductor memory device | |
| JPH0527975B2 (en) | ||
| JPH06140628A (en) | Semiconductor device and manufacture thereof | |
| JPS6276562A (en) | Semiconductor device and manufacture thereof | |
| JP3244066B2 (en) | Method for manufacturing semiconductor device | |
| JPH0226034A (en) | Manufacture of semiconductor device | |
| JPH0644604B2 (en) | Manufacturing method of complementary semiconductor device | |
| JPH11224945A (en) | Semiconductor device | |
| JPS6072271A (en) | Manufacture of semiconductor device | |
| JPH02174236A (en) | Manufacture of semiconductor device | |
| JPH05343703A (en) | Manufacture of nonvolatile memory | |
| JPH0456354A (en) | Manufacture of semiconductor device |