JPS60102745A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60102745A JPS60102745A JP21195183A JP21195183A JPS60102745A JP S60102745 A JPS60102745 A JP S60102745A JP 21195183 A JP21195183 A JP 21195183A JP 21195183 A JP21195183 A JP 21195183A JP S60102745 A JPS60102745 A JP S60102745A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- polysilicon film
- etched
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 3
- 239000007789 gas Substances 0.000 abstract 3
- 239000001301 oxygen Substances 0.000 abstract 3
- 229910052760 oxygen Inorganic materials 0.000 abstract 3
- 235000019406 chloropentafluoroethane Nutrition 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法に関し、特に半導体装
置の製造時でのポリシリコン膜のエツチング方法の改良
に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for etching a polysilicon film during the manufacturing of a semiconductor device.
従来のこの種の半導体装置の製造方法におけるポリシリ
コン膜エツチング時の状態を第1図および第2図に示し
である。すなわち、これらの各図において、符号1は半
導体基板、2はこの半導体基板1上に形成されている被
エツチング膜としてのポリシリコン膜、3はこのポリシ
リコン膜2を被覆しているパターニングされたホトレジ
スト膜などのエツチングマスクである。FIGS. 1 and 2 show the state during etching of a polysilicon film in a conventional manufacturing method of this type of semiconductor device. That is, in each of these figures, reference numeral 1 indicates a semiconductor substrate, 2 indicates a polysilicon film formed on this semiconductor substrate 1 as a film to be etched, and 3 indicates a patterned silicon film covering this polysilicon film 2. This is an etching mask such as a photoresist film.
しかして前記第1図はCF4+O2によるエツチングで
、基板1の表面が露出した瞬間にエツチングを終了させ
た場合の要部断面であシ、また前記第2図はCF4+0
2によるエツチングで、基板1の表面が露出するのに要
した時間tの2倍の時間2tまでエツチングを行なった
場合の要部断面である。However, the above-mentioned FIG. 1 shows a cross section of the main part when etching is performed using CF4+O2 and the etching is terminated at the moment the surface of the substrate 1 is exposed, and the above-mentioned FIG.
2 is a cross section of a main part when etching is performed for a time 2t, which is twice the time t required for the surface of the substrate 1 to be exposed.
これらの各図から明らかなように、従来方法でのポリシ
リコン膜のエツチングには、前記したCF4+O2のガ
スを用いているために、そのエツチングレートがせいぜ
い3,0OOA/min程度に限定されるほか、サイド
エツチング量が大きくて寸法制御が困難であるなどの不
都合を有するものであった。As is clear from these figures, since the above-mentioned CF4+O2 gas is used for etching a polysilicon film in the conventional method, the etching rate is limited to about 3,000 A/min at most. However, the amount of side etching is large and dimensional control is difficult.
この発明は従来のこのような欠点に鑑み、ポリシリコン
膜のエツチングのためにCXCtYF z 十02の混
合ガスを用いることで、同エツチングを高速かつ制御性
よく行ない得るようにしたものである。In view of these conventional drawbacks, the present invention uses a mixed gas of CXCtYF z 102 for etching a polysilicon film, thereby making it possible to perform etching at high speed and with good controllability.
以下この発明に係る半導体装置の製造方法の一実施例に
つき、第3図、第4図(a) + (b)、第5図(、
)、(C)および第6図(a) l (d)を参照して
詳細に説明する。3, FIG. 4(a) + (b), and FIG. 5(,
), (C) and FIGS. 6(a) and 6(d).
第3図はこの実施例方法に適用されるエツチング装置の
一例である。この第3図において、符号4は装置本体、
5,6は同装置本体4内に配置された1組の電極、Iは
エツチングガス導入口、8は同排出口、9は電源として
の例えば13.56 MHzの発振器である。FIG. 3 shows an example of an etching apparatus applied to this embodiment method. In this FIG. 3, numeral 4 indicates the main body of the device;
Reference numerals 5 and 6 denote a pair of electrodes arranged in the main body 4 of the apparatus, I an etching gas inlet, 8 an etching gas outlet, and 9 an oscillator of, for example, 13.56 MHz as a power source.
しかしてこのエツチング装置にC2ctF s +02
の混合ガスをインさせ、エツチング圧力0.8 Tor
r。However, in this etching device, C2ctF s +02
Etching pressure: 0.8 Torr
r.
RFパワー固定で、ポリシリコン膜をエツチングした時
の状態を第4図(a) 、 (b)ないし第6図(a)
l (b)に示しである。これらの各図中、前記第1
図および第2図と同一符号は同一または相当部分を示し
ている。Figures 4 (a), (b) to 6 (a) show the state when polysilicon film is etched with fixed RF power.
It is shown in (b). In each of these figures, the first
The same reference numerals as those in the figures and FIG. 2 indicate the same or corresponding parts.
第4図(JL) l (b)は02濃度20%、電極間
隔40順でエツチングを行なった場合の例であり、エツ
チングレートは約6,000 A/minで従来の2倍
である。同図(、)はジャストエッチ時、同図(b)は
100チオーバエツチ時のそれぞれ断面であシ、100
チオーバエツチを行なっても従来法のようにサイドエッ
チが進行せず、寸法制御の点で優れていることが判る。FIG. 4 (JL) l (b) is an example in which etching is performed at an 02 concentration of 20% and an electrode spacing of 40, and the etching rate is approximately 6,000 A/min, which is twice the conventional etching rate. The same figure (,) shows the cross section when just etching, and the same figure (b) shows the cross section when 100 th.
It can be seen that even when thiover etching is performed, side etching does not proceed as in the conventional method, and that the method is excellent in terms of dimensional control.
第5図(IL)は0□濃度20%、同図(c)はo2濃
度35チ、電極間隔40 mmでエツチングを行なった
場合の例である。エツチングレートは同図(c)におい
て約1μm/mlnにもなって従来の3倍であシ、また
そのエツチング断面も符号eのようにテーパー状に形成
される。FIG. 5 (IL) shows an example in which etching is performed at a 0□ concentration of 20%, and FIG. 5(c) shows an example in which etching is performed at an O2 concentration of 35 cm and an electrode spacing of 40 mm. The etching rate is about 1 .mu.m/mln in FIG. 1(c), which is three times that of the conventional method, and the etching cross section is also tapered as indicated by the symbol e.
第6図(、)は02濃度20%、電極間隔40mm。Figure 6 (,) shows 02 concentration of 20% and electrode spacing of 40 mm.
同図(d)は02濃度20チ、電極間隔5 mmでエツ
チングを行なった場合の例である。同図(d)においテ
ハエッチング断面が符号fのように逆テーパー状に形成
される。Figure (d) is an example of etching performed at a 02 concentration of 20 cm and an electrode spacing of 5 mm. In FIG. 3(d), the cross-section of the Tefer etching is formed in a reverse tapered shape as indicated by the symbol f.
すなわち、これらの各図から明らかなように、この実施
例方法によるときは、最高1μm/miHのエツチング
レートを得ることができ、しかもサイドエツチング量も
少なくて寸法制御性に優れており、かつまた02濃度と
か電極間隔を変化させることによシ、エツチング断面の
テーパー角についてもその制御が可能である。That is, as is clear from these figures, when using the method of this embodiment, it is possible to obtain an etching rate of up to 1 μm/miH, and the amount of side etching is also small, resulting in excellent dimensional controllability. By changing the 02 concentration or the electrode spacing, the taper angle of the etched cross section can also be controlled.
なお、前記実施例においては、エツチングガスにC2C
tF5+0□ を用いたが、その他のCxc#Fz系(
x、y、z:自然数)と02との組み合せにおいても同
様の作用、効果が得られるものである。In the above embodiment, C2C was used as the etching gas.
tF5+0□ was used, but other Cxc#Fz systems (
Similar actions and effects can be obtained by combining x, y, z: natural numbers) and 02.
以上詳述したようにこの発明方法によるときは、半導体
装置の製造に際し、ポリシリコン膜のエツチングにCX
CtYFz系(x、y、z:自然数)と02との混合ガ
スを用いるようにしたので、従来と同一のエツチング装
置によシ、同エツチング膜を高速かつ寸法制御性よく、
シかも断面形状制御のもとに効果的にエツチングするこ
とができ、その処理性能および能力を向上し得るもので
ある〇As detailed above, when using the method of the present invention, CX is used for etching a polysilicon film when manufacturing a semiconductor device.
By using a mixed gas of CtYFz series (x, y, z: natural numbers) and 02, the same etching film can be etched at high speed and with good dimensional control using the same etching equipment as before.
It can be etched effectively under cross-sectional shape control, and its processing performance and capacity can be improved.
第1図および第2図は従来例による半導体装置の製造方
法におけるポリシリコン膜エツチング時の状態を示すそ
れぞれ断面図、第3図はエツチング装置の構成例を模式
的に示す断面図、第4図(a)、(b)ないし第6図(
’) l (b)はこの発明方法の一実施例による同上
装置でのポリシリコン膜エツチング時の状態を示すそれ
ぞれ断面図である。
1・・・・半導体基板、2・・・・ポリシリコン膜、3
・・拳・エツチングマスク、4・・・Oエツチング装置
本体、5,6・―・・1組の電極、7.8・・・・ガス
導入、排出口、S・・・−発振器。
代理人大岩増雄1 and 2 are cross-sectional views showing the state during etching of a polysilicon film in a conventional semiconductor device manufacturing method, FIG. 3 is a cross-sectional view schematically showing an example of the configuration of an etching apparatus, and FIG. (a), (b) to Figure 6 (
') l (b) is a sectional view showing the state during etching of a polysilicon film using the same apparatus as described above according to an embodiment of the method of the present invention. 1... Semiconductor substrate, 2... Polysilicon film, 3
...Fist/etching mask, 4...O etching device body, 5, 6...1 set of electrodes, 7.8...Gas introduction, exhaust port, S...-oscillator. Agent Masuo Oiwa
Claims (1)
して、このポリシリコン膜をエツチングガスによシエッ
チング処理させるようにした半導体装置の製造方法にお
いて、前記エツチングガスにCXC4YFZ系(x、y
、z:自然数)と02との混合ガスを用いたことを特徴
とする半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a polysilicon film formed on a semiconductor substrate is masked and the polysilicon film is etched with an etching gas, the etching gas contains CXC4YFZ (x, y
, z: natural number) and 02.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21195183A JPS60102745A (en) | 1983-11-09 | 1983-11-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21195183A JPS60102745A (en) | 1983-11-09 | 1983-11-09 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60102745A true JPS60102745A (en) | 1985-06-06 |
Family
ID=16614392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21195183A Pending JPS60102745A (en) | 1983-11-09 | 1983-11-09 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60102745A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02280323A (en) * | 1989-04-21 | 1990-11-16 | Fuji Electric Co Ltd | Plasma etching method |
-
1983
- 1983-11-09 JP JP21195183A patent/JPS60102745A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02280323A (en) * | 1989-04-21 | 1990-11-16 | Fuji Electric Co Ltd | Plasma etching method |
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