JPH03129821A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03129821A
JPH03129821A JP26861689A JP26861689A JPH03129821A JP H03129821 A JPH03129821 A JP H03129821A JP 26861689 A JP26861689 A JP 26861689A JP 26861689 A JP26861689 A JP 26861689A JP H03129821 A JPH03129821 A JP H03129821A
Authority
JP
Japan
Prior art keywords
etching
electrode
auxiliary electrode
mode
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26861689A
Other languages
Japanese (ja)
Inventor
Masaharu Yanai
谷内 正治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26861689A priority Critical patent/JPH03129821A/en
Publication of JPH03129821A publication Critical patent/JPH03129821A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To reduce the loading effect especially generating when the density of a pattern greatly varies locally by a method wherein an etching treatment is conducted by introducing etching gas between a wafer-placed electrode and an auxiliary electrode, and deposition gas is introduced between the auxiliary electrode and the opposing electrode. CONSTITUTION:An auxiliary electrode 103 is provided between parallelplaced electrodes 101 and 102, gas introducing holes 104 and 105 are provided between the lower electrode 101 and the auxiliary electrode 103 and also between the upper electrode 102 and the auxiliary electrode 103 respectively. SF6 is introduced into a gas introducing hole 104, and CC14 is introduced into a gas introducing hole 104 respectively, and an etching treatment is conducted alternately by generating plasma. In this case, when plasma is generated between the upper electrode and the auxiliary electrode 103, a plasma etching mode (PE mode) is employed, and when plasma is generated between the lower electrode 101 and the auxiliary electrode 103, a reaction ion etching mode (RIE mode) is employed. By conducting the etching treatment using the above-mentioned PE mode and RIE mode alternately, loading effect is eliminated, and the resultant configurational difference can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にエツチング
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to etching.

〔従来の技術〕[Conventional technology]

従来このような補助電極を設けたエツチング装置は電子
の衝突確率を高め、エツチング速度を高めるという目的
のために用いられていた。
Conventionally, etching apparatuses provided with such auxiliary electrodes have been used for the purpose of increasing the probability of electron collision and increasing the etching rate.

そのためガスも補助電極の上級 下部の区別なしに導入
し高周波を印加していた0例えば、表1の条件で多結晶
シリコンをエツチングした場合、エツチング速度が42
00人/min得られ、補助電極を設けないものに比べ
て40%上昇している。しかし、このようなエツチング
ではパターンの密度によってエツチング速度が異なるロ
ーディング効果が避けられず、又、第3図のように形状
も密度によって異なっていた。
For this reason, the gas was also introduced without distinguishing between the upper and lower parts of the auxiliary electrode, and a high frequency was applied.For example, when polycrystalline silicon was etched under the conditions shown in Table 1, the etching rate was 42
00 people/min, which is 40% higher than that without auxiliary electrodes. However, in such etching, a loading effect in which the etching speed varies depending on the density of the pattern cannot be avoided, and the shape also varies depending on the density, as shown in FIG.

表1 〔発明が解決しようとする課題及び目的〕従来の技術で
はローディング効果が大きく、形状もパターンが疎のと
ころでテーパーがついてしまうという課題を有していた
Table 1 [Problems and Objectives to be Solved by the Invention] Conventional techniques had the problem of a large loading effect and a tapered shape where the pattern was sparse.

本発明はこのような課題を解決する方法を提供するもの
である。
The present invention provides a method for solving such problems.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、平行に置かれた電極
の間に補助電極を設けて高周波を印加しプラズマを発生
させエツチングを行なうドライエツチング装置において
、ウェハの置かれた電極と補助電極の間にエツチングガ
スを補助電極とウェハと対向する電極の間にデポジショ
ンガスを導入してエツチングを行なうことを特徴とする
The method for manufacturing a semiconductor device of the present invention uses a dry etching apparatus in which an auxiliary electrode is provided between electrodes placed in parallel, and a high frequency is applied to generate plasma to perform etching. The etching process is characterized in that etching is performed by introducing an etching gas between the auxiliary electrode and the electrode facing the wafer.

〔作用〕[Effect]

本発明はデポジションとエツチングを交互に行なうこと
でローディング効果が小さくなるという特徴を持ってい
るが、これはエツチング面積の大きいところではエツチ
ング速度は大きくなるのに対しデポジション速度(量)
も大きくなるし、逆に、エツチング面積の小さいところ
ではエツチング速度が小さくなるのに対しデポジション
速度も小さくなることで互いに打ち消し合っているとい
う作用を持っているからである。
The present invention has a feature that the loading effect is reduced by performing deposition and etching alternately, but this is because the etching speed increases where the etching area is large, whereas
This is because, conversely, where the etching area is small, the etching speed is low, whereas the deposition speed is also low, so they cancel each other out.

〔実施例〕〔Example〕

以上、本発明について実施例に基づき詳細に説明する。 The present invention will now be described in detail based on examples.

第1図は本発明に於いて使用したエツチング装置であり
、平行に置かれた電極(101,102)の間に補助電
極(103)が設けられており、ガス導入口(104,
105)が下部電極と補助電極の間及び上部電極と補助
電極の間にそれぞれ設けられている。
FIG. 1 shows the etching apparatus used in the present invention, in which an auxiliary electrode (103) is provided between electrodes (101, 102) placed in parallel, and a gas inlet (104,
105) are provided between the lower electrode and the auxiliary electrode and between the upper electrode and the auxiliary electrode, respectively.

このエツチング装置を用い多結晶シリコンをエツチング
する場合、ガス導入口(104)にSF6をガス導入口
(105)にCCl4を導入し、交互にプラズマをたて
てエツチングを行なう、この場合、上部電極と補助電極
の間でプラズマを発生させる場合にはプラズマエツチン
グモード(以下、PEモードと呼ぶ)となり、下部電極
と補助電極の間でプラズマを発生させる場合には反応性
イオンエツチングモード(以下、RIEモードと呼ぶ)
となる。これでCCl4のようなデポジションガスをP
Eモードでプラズマ発生を行ないデポジションを堆積さ
せ、SF6のようなエツチングガスをRIEモードでプ
ラズマ発生を行ないエツチングを行なう。このときエツ
チングをRIEモードで行なうのは異方性エツチングを
行なうためであり、デポジションガスとエツチングガス
を逆に導入すると良好なエツチングが行なわれない。
When etching polycrystalline silicon using this etching apparatus, SF6 is introduced into the gas inlet (104) and CCl4 is introduced into the gas inlet (105), and plasma is generated alternately to perform etching. When plasma is generated between the lower electrode and the auxiliary electrode, the plasma etching mode (hereinafter referred to as PE mode) is used, and when the plasma is generated between the lower electrode and the auxiliary electrode, the reactive ion etching mode (hereinafter referred to as RIE mode) is used. (called mode)
becomes. This allows the deposition gas such as CCl4 to be
Plasma is generated in E mode to deposit a deposit, and etching is performed by generating plasma in RIE mode using an etching gas such as SF6. The reason why etching is performed in RIE mode at this time is to perform anisotropic etching, and if the deposition gas and etching gas are introduced in reverse, good etching will not be performed.

表2 本実施例でエツチングを行なったときの条件は表2に示
すとおりであり、デポジションを2.5秒、エツチング
を1秒という周期で交互に行なった。
Table 2 The conditions under which etching was performed in this example are as shown in Table 2, and deposition was performed alternately at a cycle of 2.5 seconds and etching at a cycle of 1 second.

このように行なうと、従来ではエツチング面積の大きい
ところでエツチング速度が高いということが起こってい
たが、デポジションは面積の大きいところでデポジショ
ン速度が高いためデポジションとエツチングを交互に行
なうことでお互い相殺されて面積の大小に係わらず同じ
にエツチングできる。又、形状も図2のようにエツチン
グ面積の大小に係わらず垂直になる。
When performed in this way, conventionally the etching rate was high in areas where the etching area was large, but since the deposition rate is high in areas where the area is large, deposition and etching are performed alternately so that they cancel each other out. The etching process can be done in the same manner regardless of the size of the area. Also, the shape is vertical, as shown in FIG. 2, regardless of the size of the etched area.

デポジションガスとしてCCl4について述べたが実際
はこれに限るものではなく、CH2F2やCH3Fなど
でも同様の効果が得られる。
Although CCl4 has been described as the deposition gas, the deposition gas is not limited to this, and similar effects can be obtained with CH2F2, CH3F, and the like.

一方、エツチングガスもSF6に限らず、NF3などで
もよい。
On the other hand, the etching gas is not limited to SF6, but may also be NF3 or the like.

本実施例のようにトライオード型エツチング装置を用い
PEモードとRIEモードを交互に使いエツチングを行
なうことでローディング効果もなくなり、それにともな
う形状の差異もなくなる。
By performing etching using a triode type etching apparatus and alternately using PE mode and RIE mode as in this embodiment, the loading effect is eliminated, and the resulting difference in shape is also eliminated.

〔発明の効果〕〔Effect of the invention〕

本発明はパターンの疎密の激しいときに特に発生するロ
ーディング効果を低減させることができるという効果を
有している。
The present invention has the effect of being able to reduce the loading effect that occurs particularly when the pattern is highly dense and dense.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本実施例で使用したエツチング装置を示す図で
ある。 第2図は本実施例でエツチングを行なったときのエツチ
ング断面形状図である。 第3図は従来技術でエツチングを行なったときのエツチ
ング断面形状図である。 101・・・下部電極 102・・・上部電極 103・・・補助電極 104・・・ガス導入口1 105・・・ガス導入口2 106・・・ウェハー 107・・・排気口 201゜ 202゜ 203゜ 204゜ 108・・・高周波電源 301・・・レジスト 302・・・多結晶シリコン 303・・・シリコン酸化膜 304・・・シリコン基板 以上
FIG. 1 is a diagram showing an etching apparatus used in this example. FIG. 2 is an etched cross-sectional view when etching was performed in this embodiment. FIG. 3 is a cross-sectional view of etching when etching is performed using the conventional technique. 101... Lower electrode 102... Upper electrode 103... Auxiliary electrode 104... Gas inlet port 1 105... Gas inlet port 2 106... Wafer 107... Exhaust port 201°202°203゜204゜108...High frequency power supply 301...Resist 302...Polycrystalline silicon 303...Silicon oxide film 304...Silicon substrate or more

Claims (1)

【特許請求の範囲】[Claims]  平行に置かれた電極の間に補助電極を設けて高周波を
印加しプラズマを発生させエッチングを行なうドライエ
ッチング装置において、ウェハの置かれた電極と補助電
極の間にエッチングガスを、補助電極とウェハと対向す
る電極の間にデポジションガスを導入してエッチングを
行なうことを特徴とする半導体装置の製造方法。
In dry etching equipment, an auxiliary electrode is provided between electrodes placed in parallel and etching is performed by applying high frequency waves to generate plasma. A method for manufacturing a semiconductor device, characterized in that etching is performed by introducing a deposition gas between electrodes facing each other.
JP26861689A 1989-10-16 1989-10-16 Manufacture of semiconductor device Pending JPH03129821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26861689A JPH03129821A (en) 1989-10-16 1989-10-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26861689A JPH03129821A (en) 1989-10-16 1989-10-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03129821A true JPH03129821A (en) 1991-06-03

Family

ID=17461021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26861689A Pending JPH03129821A (en) 1989-10-16 1989-10-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03129821A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671152A (en) * 1995-05-19 1997-09-23 International Business Machines Corporation Efficient generation of negative fill shapes for chips and packages
US6127277A (en) * 1996-07-03 2000-10-03 Tegal Corporation Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls
KR20140082850A (en) * 2011-10-27 2014-07-02 어플라이드 머티어리얼스, 인코포레이티드 Process chamber for etching low k and other dielectric films

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671152A (en) * 1995-05-19 1997-09-23 International Business Machines Corporation Efficient generation of negative fill shapes for chips and packages
US6127277A (en) * 1996-07-03 2000-10-03 Tegal Corporation Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls
KR20140082850A (en) * 2011-10-27 2014-07-02 어플라이드 머티어리얼스, 인코포레이티드 Process chamber for etching low k and other dielectric films
JP2014532988A (en) * 2011-10-27 2014-12-08 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Process chamber for etching low K and other dielectric films
CN106876264A (en) * 2011-10-27 2017-06-20 应用材料公司 Process chamber for etching low k and other dielectric films
JP2018050055A (en) * 2011-10-27 2018-03-29 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Process chambers for etching low-k and other dielectric films
US10096496B2 (en) 2011-10-27 2018-10-09 Applied Materials, Inc. Process chamber for etching low K and other dielectric films
CN110289233A (en) * 2011-10-27 2019-09-27 应用材料公司 For etching the process chamber of low K and other dielectric films
JP2019179921A (en) * 2011-10-27 2019-10-17 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Process chambers for etching low k and other dielectric films
KR20200037451A (en) * 2011-10-27 2020-04-08 어플라이드 머티어리얼스, 인코포레이티드 Process chamber for etching low k and other dielectric films
JP2020074452A (en) * 2011-10-27 2020-05-14 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Processing chamber for etching low k and another dielectric film
US10923367B2 (en) 2011-10-27 2021-02-16 Applied Materials, Inc. Process chamber for etching low K and other dielectric films
US11410860B2 (en) 2011-10-27 2022-08-09 Applied Materials, Inc. Process chamber for etching low k and other dielectric films

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