JPS61172333A - Semiconductor manufacturing equipment - Google Patents

Semiconductor manufacturing equipment

Info

Publication number
JPS61172333A
JPS61172333A JP1382185A JP1382185A JPS61172333A JP S61172333 A JPS61172333 A JP S61172333A JP 1382185 A JP1382185 A JP 1382185A JP 1382185 A JP1382185 A JP 1382185A JP S61172333 A JPS61172333 A JP S61172333A
Authority
JP
Japan
Prior art keywords
electrode
electrodes
etching
semiconductor
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1382185A
Other languages
Japanese (ja)
Inventor
Kenichi Hatasako
畑迫 健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1382185A priority Critical patent/JPS61172333A/en
Publication of JPS61172333A publication Critical patent/JPS61172333A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To etch a plurality of semiconductors by one time processing making the etching process faster and more efficient by a method wherein a plurality of high frequency electrodes or grounding electrodes are provided on a semiconductor manufacturing equipment be processed by plasma. CONSTITUTION:An electrode 10b out of three electrodes is connected to a high- frequency electrode 4 and the other two electrodes 10a, 10c are grounded while a semiconductor substrate 7 is mounted on the surface and backside of electrode 10b connected to the high-frequency electrode 4. The electrode 10b is impressd with high voltage from the high-frequency electrode 4 to produce plasma in an etching chamber 3. The semiconductor suhbstrate 7 mounted on both sides of electrode 10b is etched by plasma. Through these procedures, etching speed may be accelerated to miniaturize the device in terms of the quantity to be processed since more than three each of electrodes are utilized to process more than two each of semiconductor substrates in total mounted on an electrode.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体製造装置に関し、特にプラズマによる
エツチング装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor manufacturing equipment, and more particularly to an etching equipment using plasma.

〔従来の技術〕[Conventional technology]

従来のプラズマエッチング装置の構造の例として、枚葉
式エツチング装置の構造を第6図に示し、第7図に第6
図の枚葉式エツチング装置の電極方式を変えた他の構造
を示す。第61!l及び第7図において、1,2はそれ
ぞれ高周波電圧を印加するための上部電極、下部電極、
3はエツチング室であるチャンバー、4は高周波電源、
5は電源ケーブル、7は半導体基板である。
As an example of the structure of a conventional plasma etching apparatus, the structure of a single wafer type etching apparatus is shown in FIG.
This figure shows another structure in which the electrode system of the single-wafer etching apparatus shown in the figure is changed. 61st! 1 and FIG. 7, 1 and 2 are an upper electrode and a lower electrode for applying a high frequency voltage, respectively.
3 is a chamber which is an etching chamber, 4 is a high frequency power supply,
5 is a power cable, and 7 is a semiconductor substrate.

次に動作について説明する。第6.7図において、下部
電極2の上に半導体基板7を置き、チャンバー3の内部
を排気した後、チャンバー3の内部にガスを流入する(
排気口及びガス流入口は図示せず)。ガスの圧力が一定
点に達した時点で高周波電源4より上、下部電極1.2
の両電極間に高電圧を印加し、チャンバー3内にプラズ
マを発生させる。発生したプラズマにより半導体基板7
あるいは半導体基板7上に形成されたポリシリコンなど
の被エツチング物を所定の形状にエツチングする。
Next, the operation will be explained. In FIG. 6.7, the semiconductor substrate 7 is placed on the lower electrode 2, the inside of the chamber 3 is evacuated, and then gas is flowed into the inside of the chamber 3 (
(Exhaust port and gas inlet are not shown). When the gas pressure reaches a certain point, the upper and lower electrodes 1.2
A high voltage is applied between both electrodes to generate plasma within the chamber 3. The generated plasma causes the semiconductor substrate 7 to
Alternatively, an object to be etched such as polysilicon formed on the semiconductor substrate 7 is etched into a predetermined shape.

第6図の場合、上部電極1に高周波電源4が印加され、
下部電極2は接地されている。第7図はその逆である。
In the case of FIG. 6, a high frequency power source 4 is applied to the upper electrode 1,
The lower electrode 2 is grounded. Figure 7 shows the opposite.

両者において印加電極の相違はプラズマイオンの動きの
相違となり、エツチング特性が異なることなるが、動作
原理は同じである。
In both cases, the difference in the application electrode results in a difference in the movement of plasma ions, resulting in different etching characteristics, but the operating principle is the same.

第8図は多数個の半導体基板をエツチングするバッチ式
のエツチング装置を示す。図において、4.5.7は上
記と同しで、8は六角柱状の内部電極であり、これに半
導体基板7を複数個取付けている。9は円筒形チャンバ
ーである。
FIG. 8 shows a batch type etching apparatus for etching a large number of semiconductor substrates. In the figure, 4.5.7 is the same as above, and 8 is a hexagonal column-shaped internal electrode, to which a plurality of semiconductor substrates 7 are attached. 9 is a cylindrical chamber.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかるに上記第6図、第7図に示す従来の半導体製造装
置では、エツチングに際し、チャンバー3内に置く半導
体基板7は1枚のみであり、エツチング室程の能率は著
しく低かった。また第8図の半導体基板を複数個エツチ
ングするバッチ式のものでは、内部電極8が大型化し、
スペース上の効率の低下や装置の複雑性が増すという欠
陥があった・ この発明は上記のような従来の問題点を解決するために
なされたもので、−回の処理で複数の半導体基板をエツ
チングできる半導体製造装置を提供することを目的とす
る。
However, in the conventional semiconductor manufacturing apparatus shown in FIGS. 6 and 7, only one semiconductor substrate 7 is placed in the chamber 3 during etching, and the efficiency is significantly lower than that of an etching chamber. Furthermore, in the batch type etching method shown in FIG. 8, in which multiple semiconductor substrates are etched, the internal electrodes 8 become larger
This invention was made to solve the above-mentioned conventional problems, and it is possible to process multiple semiconductor substrates in one process. The object of the present invention is to provide a semiconductor manufacturing device that can perform etching.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体製造装置は枚葉式の電極ではなく
、高周波電極ないしは接地電極を複数個設け、該電極に
合計で少なくとも2個以上の半導体基板を取付け、1個
の装置で複数の半導体基板をエツチング処理するもので
ある。
The semiconductor manufacturing apparatus according to the present invention is not equipped with single-wafer type electrodes, but is provided with a plurality of high-frequency electrodes or ground electrodes, and a total of at least two or more semiconductor substrates are attached to the electrodes, so that one apparatus can manufacture a plurality of semiconductor substrates. This is an etching process.

〔作用〕[Effect]

この発明における半導体製造装置は、31[1!1以上
の電極を設け、該電極に合計で少なくとも2個以上の半
導体基板を装着し同時に処理するから、エツチング処理
を高速化、能率化できる。
The semiconductor manufacturing apparatus according to the present invention is provided with 31[1!1 or more electrodes, and a total of at least two or more semiconductor substrates are mounted on the electrodes and processed simultaneously, so that the etching process can be made faster and more efficient.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、3はエツチング室を形成するチャンバー、
4は高周波電源、10a、10b。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 3 is a chamber forming an etching chamber;
4 is a high frequency power source, 10a, 10b.

10cは3枚設けられた電極、7はエツチングすべき半
導体基板であり、これはシリコンウェハやシリコンウェ
ハ上に形成されたポリシリコンなどの被エツチング物で
ある。また5は電源ケーブルである。
Reference numeral 10c indicates three electrodes, and 7 indicates a semiconductor substrate to be etched, which is an object to be etched such as a silicon wafer or polysilicon formed on a silicon wafer. Further, 5 is a power cable.

図において、3枚の電極のうち電極10bは高周波電源
4に接続され、他の2枚の電極10a。
In the figure, among the three electrodes, the electrode 10b is connected to the high frequency power source 4, and the other two electrodes 10a.

10cは接地されており、半導体基板7は高周波電源4
に接続された電極10bの表裏に装着されている。
10c is grounded, and the semiconductor substrate 7 is connected to the high frequency power source 4.
The electrodes 10b are attached to the front and back sides of the electrode 10b connected to the electrode 10b.

次に動作について説明する。Next, the operation will be explained.

まずチャンバー3の内部を排気し、チャンバ−3内部に
ガスを流入し圧力が一定した時点で、高周波電源4より
電極10bに高電圧を印加し、エツチング室3内にプラ
ズマを発生させる。このプラズマにより、電極lObの
両面に取付けられた半導体基板7をエツチングする。
First, the inside of the chamber 3 is evacuated, gas is introduced into the chamber 3, and when the pressure becomes constant, a high voltage is applied to the electrode 10b from the high frequency power source 4 to generate plasma in the etching chamber 3. This plasma etches the semiconductor substrate 7 attached to both sides of the electrode lOb.

上記実施例では半導体基板7を高周波電源4に接続され
た電極10bに取付けたが、これは第2図に示すように
、接地電極10a、10cに半導取付けてもよい。
In the above embodiment, the semiconductor substrate 7 is attached to the electrode 10b connected to the high frequency power source 4, but the semiconductor substrate 7 may be attached to the ground electrodes 10a and 10c as shown in FIG.

これらの実施例では複数の高周波電界の印加された電極
ないしは接地電極の表裏に被エツチング物を装着してい
るので、従来の2倍以上の速度で−エツチング処理がで
き、処理枚数に対し装置は比較的小型化したといえる。
In these embodiments, the objects to be etched are mounted on the front and back surfaces of multiple electrodes to which high-frequency electric fields are applied or ground electrodes, so etching can be performed at more than twice the speed of conventional etching, and the equipment required for the number of sheets to be processed is reduced. It can be said that it has become relatively compact.

また以上は半導体基板のエツチングのみについて記した
が、半導体基板上の金属膜、絶縁膜、その他の半導体製
造に使用される被エツチング物のエツチングの場合であ
ってもよい。
Further, although the above description has only been about etching of a semiconductor substrate, the present invention may also be applied to etching of a metal film, an insulating film, or other objects to be etched used in the manufacture of semiconductors on a semiconductor substrate.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、電極の枚数を3個以
上にし、該電極に合計で少なくとも2個以上の半導体基
板を取付けて処理するようにしたので、エツチング処理
速度が上がり、また処理枚数に比し装置は小型化すると
いう効果がある。
As described above, according to the present invention, the number of electrodes is increased to three or more, and a total of at least two or more semiconductor substrates are attached to the electrodes for processing, so that the etching processing speed is increased and the processing speed is increased. This has the effect of reducing the size of the device compared to the number of sheets.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体製造装置を示
す構成図、第2図、第3図はこの発明の他の実施例を示
す構成図、第4図、第5図は本宛装置を示す構成図であ
る。 1旧・・電極、3・・・チャンバー1.4・・・高周波
電源、5・・・電源ケーブル、7・・・半導体基板。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing a semiconductor manufacturing apparatus according to one embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing other embodiments of the present invention, and FIGS. 4 and 5 are block diagrams showing a book destination apparatus. FIG. 1. Old electrode, 3. Chamber 1.4. High frequency power supply, 5. Power cable, 7. Semiconductor substrate. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体をプラズマによって処理する半導体製造装
置において、高周波電圧が印加される3個以上の電極を
設け、1個以上の該電極に半導体基板を複数個取付ける
ことを特徴とする半導体製造装置。
(1) A semiconductor manufacturing apparatus for processing semiconductors using plasma, characterized in that three or more electrodes to which a high frequency voltage is applied are provided, and a plurality of semiconductor substrates are attached to one or more of the electrodes.
JP1382185A 1985-01-28 1985-01-28 Semiconductor manufacturing equipment Pending JPS61172333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1382185A JPS61172333A (en) 1985-01-28 1985-01-28 Semiconductor manufacturing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1382185A JPS61172333A (en) 1985-01-28 1985-01-28 Semiconductor manufacturing equipment

Publications (1)

Publication Number Publication Date
JPS61172333A true JPS61172333A (en) 1986-08-04

Family

ID=11843938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1382185A Pending JPS61172333A (en) 1985-01-28 1985-01-28 Semiconductor manufacturing equipment

Country Status (1)

Country Link
JP (1) JPS61172333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100500432B1 (en) * 2002-09-26 2005-07-14 주식회사 피에스엠 Atmospheric plasma apparatus using radical self-flow electrode structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100500432B1 (en) * 2002-09-26 2005-07-14 주식회사 피에스엠 Atmospheric plasma apparatus using radical self-flow electrode structure

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