JPS596543A - Etching method and device therefor - Google Patents

Etching method and device therefor

Info

Publication number
JPS596543A
JPS596543A JP11543882A JP11543882A JPS596543A JP S596543 A JPS596543 A JP S596543A JP 11543882 A JP11543882 A JP 11543882A JP 11543882 A JP11543882 A JP 11543882A JP S596543 A JPS596543 A JP S596543A
Authority
JP
Japan
Prior art keywords
etching
chamber
wafer
magnetic field
frequency electric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11543882A
Other languages
Japanese (ja)
Inventor
Tsutomu Okabe
勉 岡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11543882A priority Critical patent/JPS596543A/en
Publication of JPS596543A publication Critical patent/JPS596543A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enhance precision of etching by applying a magnetic field from the circumference to ionic reaction nuclei for etching. CONSTITUTION:When high-frequency electric power is applied to parallel plane electrodes 2, 3 in a chamber 1 by a high-frequency electric power source 4, a high-frequency electric field is generated between the electrodes 2, 3 to generate gas plasma, and because CF4 is used as reaction gas, CF3<+> is generated as the ionic reaction nucleus, and anisotropic etching is performed to the poly-silicon film or the SiO2 film of a wafer 5. Because the magnetic field is applied from all directions of the outside circumferential side of the chamber 1 according to a coil 7, force toward the central direction of the chamber 1 is applied to CF3<+>, and CF3<+> is concentrted to the upper part of the wafer 5. Accordingly, the quantities of CF3<+> to contribute to etching reaction of the wafer 5 is increased, and the etching rate is enhanced.

Description

【発明の詳細な説明】 本発明は半導体基板(ウェハ)にエツチング処理を施こ
すためのエツチング方法および装置に関し、特に、能率
良くエツチングを行なうことのできるエツチング方法お
よび装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an etching method and apparatus for etching a semiconductor substrate (wafer), and more particularly to an etching method and apparatus capable of etching efficiently.

従来、半導体製品の製造過程においてウェハに対してポ
リシリコン膜、Sin、膜にエツチング処理を施こす場
合、たとえば平行平板電極を用いてガスプラズマエツチ
ングを行なう方式が採用されている。その場合、エツチ
ング用のプラズマガスとし℃四フッ化メタン(CF4)
を用いるときには、イオン性反応種とし−(F+または
CF:が考えられる。
Conventionally, in the process of manufacturing semiconductor products, when etching a polysilicon film, a Si film, or a film on a wafer, a method has been adopted in which gas plasma etching is performed using, for example, parallel plate electrodes. In that case, the plasma gas for etching is °C tetrafluoromethane (CF4).
When using -(F+ or CF:) as the ionic reactive species.

また、エツチングには異方性と等方性があり、異方性エ
ツチングではイオン性反応種としてCFs+を利用して
いるが、等方性エツチングではF”を利用する。その場
合に1等方性エツチングではオーバーエッチ量の制御が
困難であるが、異方性エツチングでは制御が容易であり
、エツチング精度の向上にも適しているが、エッチレー
トが比較的低いという問題がある。一方、等方性エツチ
ングの場合にも、エツチング精度を向上させることが望
まれている。
In addition, there are two types of etching: anisotropic and isotropic. In anisotropic etching, CFs+ is used as an ionic reactive species, but in isotropic etching, F" is used. With anisotropic etching, it is difficult to control the amount of overetching, but with anisotropic etching, it is easy to control and is suitable for improving etching accuracy, but there is a problem that the etch rate is relatively low.On the other hand, etc. Even in the case of directional etching, it is desired to improve the etching accuracy.

したがって1本発明の目的は、前記従来技術の課題に鑑
みてなされたもので、エツチングレートな向上させ、能
率の良いエツチングが可能であり。
Therefore, one object of the present invention is to improve the etching rate and enable efficient etching.

エツチング精度を向上させることの可能なエツチング方
法および装置を提供することKある。
It is an object of the present invention to provide an etching method and apparatus that can improve etching accuracy.

この目的を達成するため1本発明はエツチング用のイオ
ン性反応種に対して周囲から磁界を印加し、イオン性反
応種を半導体基板(ウェハ)のエツチングのために集中
的に有効利用するものである。
In order to achieve this object, the present invention applies a magnetic field from the surroundings to ionic reactive species for etching, and effectively utilizes the ionic reactive species intensively for etching a semiconductor substrate (wafer). be.

以下1本発明を図面に示す一実施例にしたがって詳細に
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below according to an embodiment shown in the drawings.

第1図は本発明によるエツチング装置の一実施例を示す
概略的縦断面図、第2図はその水平断面図である。
FIG. 1 is a schematic vertical sectional view showing an embodiment of an etching apparatus according to the present invention, and FIG. 2 is a horizontal sectional view thereof.

本実施例において、エツチング用のチャンバlの中には
平行平板電極2.3が水平方向に配置され、これらの平
行平板電極2.3はプラズマ発生用の高周波電源4&C
接続されている。エツチング処理されるウェハ5は平行
平板電極3上に置かれている。
In this embodiment, parallel plate electrodes 2.3 are arranged horizontally in the etching chamber l, and these parallel plate electrodes 2.3 are connected to a high frequency power source 4&C for plasma generation.
It is connected. A wafer 5 to be etched is placed on parallel plate electrodes 3.

前記チャンバ1の底壁には排気管6が複数本接続され、
これらの排気管6は図示しない真空源に連通し工いる。
A plurality of exhaust pipes 6 are connected to the bottom wall of the chamber 1,
These exhaust pipes 6 are connected to a vacuum source (not shown).

さらに1本実施例においては、ウェハ5のほぼ水平方向
やや上方、すなわち平行平板電極2.3の間の位置にお
けるチャンバ1の外側には、磁界発生手段としてのコイ
ル7が4個互いに直角に配設されている。これらのコイ
ル7はウェハ5のボ11シリコン、Sin、のエツチン
グに用いられるCF、ガスのCF−を磁界によりチャン
バ1の中心方向すなわちウェハ5の方向に移動させ、エ
ツチングのための反応に寄与するイオン性反応種(本実
施例ではcps)の量をできるだけ多くし、エツチング
レートな向上させるためのものである。
Furthermore, in this embodiment, four coils 7 as magnetic field generating means are arranged at right angles to each other on the outside of the chamber 1 at a position slightly above the wafer 5 in the horizontal direction, that is, between the parallel plate electrodes 2.3. It is set up. These coils 7 use a magnetic field to move the gas CF-, which is used for etching the silicon (Si) on the wafer 5, toward the center of the chamber 1, that is, toward the wafer 5, and contribute to the reaction for etching. This is to increase the amount of ionic reactive species (cps in this example) as much as possible to improve the etching rate.

次に1本実施例の作用について説明する。Next, the operation of this embodiment will be explained.

高周波電源4でチャンバ1内の平行平板電極2゜3に高
周波電力を印加すると、両電極2.3間には高周波電界
が発生され、ガスプラズマが発生される。この実施例で
は、エツチング用の反応ガスとしてCF4が用いられて
いるので、チャンバ1内にはイオン性反応種としてCF
tが発生し、このCFs+を用いてウェハ5のポリシリ
コン膜またはSly、膜に対し異方性エツチングが行わ
れる。
When high frequency power is applied to the parallel plate electrodes 2.3 in the chamber 1 by the high frequency power source 4, a high frequency electric field is generated between the two electrodes 2.3, and gas plasma is generated. In this example, since CF4 is used as the reactive gas for etching, CF4 is used as the ionic reactive species in the chamber 1.
t is generated, and the polysilicon film or Sly film of the wafer 5 is anisotropically etched using this CFs+.

その場合1本実施例では、コイル7によりチャンバ1の
外周側の四方から磁界が印加されるので。
In this case, in this embodiment, a magnetic field is applied from all sides of the outer circumference of the chamber 1 by the coil 7.

チャンバ1内のCF−には咳チャンバ1の中心方向への
力が加えられ、CFtはチャンバ1の中心部すなわちウ
ェハ5の上方に集中する。
A force is applied to the CF− in the chamber 1 toward the center of the cough chamber 1, and the CFt is concentrated in the center of the chamber 1, that is, above the wafer 5.

したがって、本実施例においては、ウェハ5のエツチン
グ反応に寄与するCFtの量が増加し。
Therefore, in this embodiment, the amount of CFt contributing to the etching reaction of the wafer 5 increases.

エツチングレートが向上する。その結果、エツチングの
能率が良く、処理枚数が増加し、またエツチング精度が
向上する。特に、異方性エツチングを行なう場合には、
等方性エツチングの場合に比してエツチング精度の向上
がより大きく、極めて良好なエツチング精度が得られる
ので、歩留りの向上も図ることができる。
Etching rate is improved. As a result, etching efficiency is improved, the number of sheets processed increases, and etching accuracy improves. Especially when performing anisotropic etching,
The improvement in etching accuracy is greater than in the case of isotropic etching, and extremely good etching accuracy can be obtained, so that the yield can also be improved.

なお、コイル7により印加される磁界の向きは平行平板
電極2.3間に印加される電界の方向が逆方向になった
場合にはそれに応じて変え、常にチャンバlの中心部へ
の力が加わるよう制御される。
Note that the direction of the magnetic field applied by the coil 7 is changed accordingly when the direction of the electric field applied between the parallel plate electrodes 2 and 3 is reversed, so that the force toward the center of the chamber l is always maintained. controlled to participate.

また、エツチング用のガスとしてはCF4の他に、 C
CA 、 B (’g、の如き塩素系ガス等、様々なガ
スを用いることができる。
In addition to CF4, C
Various gases can be used, such as chlorine-based gases such as CA, B ('g, etc.).

本発明は異方性1等方性を問わず、イオンを利用するエ
ツチング技術全般に適用でき、微細エツチング加工にも
好適である。
The present invention is applicable to all etching techniques using ions, regardless of anisotropy, and is also suitable for fine etching processing.

以上説明したように、本発明によれば、エツチングレー
トな向上させ、能率良くエツチングを行なうことができ
ろう
As explained above, according to the present invention, it is possible to improve the etching rate and perform etching efficiently.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるエツチング装置の一実施例を示す
概略的縦断面図、 第2図はその水平断面図である。 1・・・チャンバ、2.3・・・平行平板電極、4・・
・高周波電源、5・・・ウェハ、6・・・排気管、7・
・・コイル(磁界発生手段)。 代理人 弁理士  薄 1)利 幸、
FIG. 1 is a schematic vertical sectional view showing an embodiment of an etching apparatus according to the present invention, and FIG. 2 is a horizontal sectional view thereof. 1... Chamber, 2.3... Parallel plate electrode, 4...
・High frequency power supply, 5... wafer, 6... exhaust pipe, 7.
... Coil (magnetic field generating means). Agent Patent Attorney Susuki 1) Toshiyuki,

Claims (1)

【特許請求の範囲】 1、イオン性反応種を用い℃半導体基板のエツチングを
行なう方法におい工、イオン性反応糧に対1−て周囲方
向から磁界を印加しながらエツチングすることを特徴と
するエツチング方法。 2、イオン性反応種を用いてチャンバ内の半導体基板に
エツチングを行なう装置において、半導体基板を収容し
たチャンバの周囲側に磁界発生手段を配設したことを特
徴とするエツチング装置。
[Claims] 1. A method for etching a semiconductor substrate at °C using an ionic reactant; 1. An etching process characterized by etching the ionic reactant while applying a magnetic field from the surrounding direction; Method. 2. An etching apparatus for etching a semiconductor substrate in a chamber using ionic reactive species, characterized in that a magnetic field generating means is disposed around the chamber containing the semiconductor substrate.
JP11543882A 1982-07-05 1982-07-05 Etching method and device therefor Pending JPS596543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11543882A JPS596543A (en) 1982-07-05 1982-07-05 Etching method and device therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11543882A JPS596543A (en) 1982-07-05 1982-07-05 Etching method and device therefor

Publications (1)

Publication Number Publication Date
JPS596543A true JPS596543A (en) 1984-01-13

Family

ID=14662556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11543882A Pending JPS596543A (en) 1982-07-05 1982-07-05 Etching method and device therefor

Country Status (1)

Country Link
JP (1) JPS596543A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62195122A (en) * 1985-11-29 1987-08-27 マテリアルズ リサーチ コーポレイション Plasma processing apparatus with magnified magnetic field
JPS62218586A (en) * 1986-03-19 1987-09-25 Anelva Corp Plasma treating device
JPS63278339A (en) * 1986-12-19 1988-11-16 アプライド マテリアルズインコーポレーテッド Bromine and iodine etching for silicon and silicide

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62195122A (en) * 1985-11-29 1987-08-27 マテリアルズ リサーチ コーポレイション Plasma processing apparatus with magnified magnetic field
JPS62218586A (en) * 1986-03-19 1987-09-25 Anelva Corp Plasma treating device
JPS63278339A (en) * 1986-12-19 1988-11-16 アプライド マテリアルズインコーポレーテッド Bromine and iodine etching for silicon and silicide
US6020270A (en) * 1986-12-19 2000-02-01 Applied Materials, Inc. Bomine and iodine etch process for silicon and silicides

Similar Documents

Publication Publication Date Title
JP5296380B2 (en) Plasma processing step set adjustment method
JP5219479B2 (en) Uniformity control method and system in ballistic electron beam enhanced plasma processing system
JP3920015B2 (en) Si substrate processing method
JP2016154234A (en) Material processing for realizing sub 10 nm patterning
JP6779846B2 (en) In-situ spacer reshaping method and system for self-aligned multi-patterning
US20100081287A1 (en) Dry etching method
JPH03218627A (en) Method and device for plasma etching
JPS58157975A (en) Plasma etching method
JPH0359573B2 (en)
JP4387801B2 (en) Semiconductor wafer dry etching method
KR102455749B1 (en) Method for increasing oxide etch selectivity
JPS596543A (en) Etching method and device therefor
US9349574B2 (en) Plasma etching method and plasma etching apparatus
JP5264383B2 (en) Dry etching method
TW201829835A (en) Method for processing object to be processed
JPH02312231A (en) Dryetching device
JPH0573051B2 (en)
JP4865951B2 (en) Plasma etching method
JPH10270429A (en) Plasma treating device
JP5207892B2 (en) Dry etching method
JPS6094724A (en) Dry etching device
JP2794963B2 (en) Dry etching method and dry etching apparatus
JPH05144773A (en) Plasma etching apparatus
JP2023032693A (en) Etching method and plasma etching device
JPH04317324A (en) Method and apparatus for producing plasma