JPS62106629A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62106629A
JPS62106629A JP24619385A JP24619385A JPS62106629A JP S62106629 A JPS62106629 A JP S62106629A JP 24619385 A JP24619385 A JP 24619385A JP 24619385 A JP24619385 A JP 24619385A JP S62106629 A JPS62106629 A JP S62106629A
Authority
JP
Japan
Prior art keywords
etching
pattern
gas
isotropic etching
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24619385A
Other languages
Japanese (ja)
Other versions
JPH051978B2 (en
Inventor
Yoshie Tanaka
田中　佳恵
Kotaro Fujimoto
幸太郎 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Plant Technologies Ltd
Original Assignee
Hitachi Techno Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Techno Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Techno Engineering Co Ltd
Priority to JP24619385A priority Critical patent/JPS62106629A/en
Publication of JPS62106629A publication Critical patent/JPS62106629A/en
Publication of JPH051978B2 publication Critical patent/JPH051978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Abstract

PURPOSE:To form a pattern with a tapering side surface and to suppress the reduction in the throughput by a method wherein an anisotropic etching is performed using halogen gas after an isotropic etching is performed using fluorine gas not containing carbon. CONSTITUTION:An isotropic etching is performed on an upper part of a polycrystalline silicon layer 4. Whereupon, a configuration W2 of the upper part of the silicon layer 4 becomes larger than a configuration W1 of an aperture of a pattern 3. Then, an anisotropic etching is performed on a lower part of the silicon layer 4. Whereupon, a vertical etching side surface of the same configuration as the aperture configuration W1 of the pattern 3 is obtained. Hereby, a tapering and microscopic pattern is formed. Consequently, the reduction in the throughput is suppressed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装ガの製造方法に係り、特に半導体基
板上の多結晶シリコン膜にテーパ状の側面をもつパター
ンを形成するのに好適な半導体装置の製造方法に関する
ものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method suitable for forming a pattern with tapered side surfaces on a polycrystalline silicon film on a semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device.

〔発明の背景〕[Background of the invention]

半導体基板上の多結晶シリコン膜にテーパ状の側面をも
つパターンを形成する方法としては、例えば、特り月昭
５７−７９３６号公報に記載のような、エツチングガス
にＣＦａ　＋　０２またはＣＦ’４＋０２　Ｆ４　Ｃ／
を用いて等方性エツチングを行い、引続いて、エツチン
グガスＣＣＺ４やＰＣｌ３　　を用いて異方性エツチン
グを行うようにした方法が知られている。A method for forming a pattern with tapered side surfaces on a polycrystalline silicon film on a semiconductor substrate is, for example, using CFa + 02 or CF'4 + 02 as an etching gas, as described in Japanese Patent No. 57-7936. F4 C/
A known method is to perform isotropic etching using etching gas CCZ4 or PCl3, followed by anisotropic etching using etching gas CCZ4 or PCl3.

しかし、このような方法では、等方性エツチング時にエ
ツチング面に炭素のデポが生成してエツチング速度が低
下しスループットが低下するといった問題がある。However, such a method has a problem in that carbon deposits are formed on the etched surface during isotropic etching, resulting in a decrease in etching rate and throughput.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、等方性エツチング時のエッチｆζＰ ング速度の低下をノ制することで、スルーブツトの低下
を抑制できる半導体装置の製造方法を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress a decrease in throughput by suppressing a decrease in etch fζP rate during isotropic etching.

〔発明のＲ要〕[Requirements for invention]

本発明は、半導体装置の製造方法を、炭素を含まないフ
ッ素系ガスを用いて等方性エツチングを行った後に、ハ
ロゲンガスを用いて異方性エツチングを行い半導体基板
上の多結晶シリコン膜にテーパ状の側面をもつパターン
を形成する方法とすることで、等方性エツチング時にお
けるエツチング面での炭素のデポの生成を防止して等方
性エツチング時のエツチング速度の低下を抑制しようと
するものである。The present invention provides a method for manufacturing a semiconductor device in which isotropic etching is performed using a fluorine-based gas that does not contain carbon, and then anisotropic etching is performed using halogen gas to form a polycrystalline silicon film on a semiconductor substrate. By forming a pattern with tapered side surfaces, we are attempting to prevent the formation of carbon deposits on the etching surface during isotropic etching, thereby suppressing the decrease in etching speed during isotropic etching. It is something.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第１図〜第４図により説明する
。第１図は平板型リアクティブイオンエツチング装置で
、ｉ！極極上上ウェハｌＯを保持し対向電極Ｂとの間に
１３．５６　ＭＨｚ　　の高周波電力を印加し、ガス導
入口Ｃにより反応ガスを供給する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 4. Figure 1 shows a flat plate type reactive ion etching device, i! A high frequency power of 13.56 MHz is applied between the topmost wafer IO and the counter electrode B, and a reaction gas is supplied through the gas inlet C.

このような装置において、多結晶シリコンをエツチング
する実施例の工程断面図を第２図〜第４図（こ示してい
る。図において、４は多結晶シリコン）１１（厚さ約４
０００Ａ）でその上にフォトレジスト膜のパターン３が
形成されている。上記装置により、多結晶シリコン層４
の上部２０００Ａに等方性エツチングを施す。その条件
は、反応ガスとして炭素を含まないフッ素系ガス、例え
ば、ＳＦ６を使用し、高周波電力１６０Ｗ、圧力０．２
〜０．４Ｔｏｒｒで処理する。そうすると、等方性エツ
チングによりサイドエツチングがなされ第３図に示すよ
うに多結晶シリコン層４上部の形状Ｗ２はパターン３の
開口部形状Ｗ、より大きくなる。In such an apparatus, process cross-sectional views of an embodiment of etching polycrystalline silicon are shown in FIGS.
000A), and a photoresist film pattern 3 is formed thereon. With the above device, the polycrystalline silicon layer 4
Isotropic etching is applied to the upper part 2000A of the . The conditions were to use a carbon-free fluorine gas such as SF6 as the reaction gas, high frequency power of 160 W, and pressure of 0.2
Process at ~0.4 Torr. Then, side etching is performed by isotropic etching, and the shape W2 of the upper part of the polycrystalline silicon layer 4 becomes larger than the shape W of the opening of the pattern 3, as shown in FIG.

次に、同一装置内において多結晶シソコン層４の下層部
に異方性エツチングを施す。そのエツチング条件は、反
応ガスとしてハロゲンガス、例えば、ＣＣ１，、を使用
し、圧力０．２　Ｔｏｒｒ高周波１力２００Ｗで処理す
る。そうすると異方性エツチングによりパターン３の開
口部形状ｗｌと同形の垂直なエツチング側面が得られる
。このように、同一装置内で等方性エツチング続いて異
方性エツチングを施して、第４図のようなテーバ状で微
細化されたパターンが形成される。Next, the lower part of the polycrystalline silicon layer 4 is anisotropically etched in the same apparatus. The etching conditions are as follows: a halogen gas, for example CC1, is used as a reaction gas, and the process is carried out at a pressure of 0.2 Torr and a high frequency power of 200 W. Then, by anisotropic etching, a vertical etched side surface having the same shape as the opening shape wl of pattern 3 can be obtained. In this manner, isotropic etching followed by anisotropic etching is performed in the same apparatus, thereby forming a tapered and fine pattern as shown in FIG.

本実施例では、次のような効果が得られる。In this embodiment, the following effects can be obtained.

（１）等方性エツチング時にエツチング面に炭素のテ゛
ボが形成されないため、この時のエツチング速度の低下
を抑制できスループットの低下を抑制できる。(1) Since no carbon holes are formed on the etched surface during isotropic etching, it is possible to suppress a decrease in the etching rate at this time and to suppress a decrease in throughput.

（２）　　同一装置内で等方性エツチングと異方性エツ
チングを行うため、この分、処理を要する時間を短縮で
きスループットを向上できる。(2) Since isotropic etching and anisotropic etching are performed in the same device, the time required for processing can be shortened and throughput can be improved.

なお、異方性エツチング用のガスとしては、別ＣＩ！４
を用いても良い。In addition, as a gas for anisotropic etching, another CI! 4
You may also use

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、等方性エツチング時の
エツチング速度の低下を抑制できスループットの低下を
抑制できるという効果がある。As explained above, the present invention has the effect of suppressing a decrease in etching rate during isotropic etching and suppressing a decrease in throughput.

【図面の簡単な説明】[Brief explanation of drawings]

ｉ１図〜第４図は、本発明の一実施例を説明するもので
、′＠１図は、平行平板型リアクティブイオンエツチン
グ装置の構成図、第２図〜第４図は、工程順の断面図で
ある。 工・・・・・・ウェハ、３・・・・・・パターン、４・
・−・・多結晶代理人　弁理士　　小　川　勝　男□ 才２図 才３図 Ｗ。 第４図Figure i1 to Figure 4 explain one embodiment of the present invention. Figure 1 is a block diagram of a parallel plate type reactive ion etching apparatus, and Figures 2 to 4 are diagrams showing the order of steps. FIG. Process: wafer, 3: pattern, 4:
--- Polycrystalline agent, patent attorney Masaru Ogawa, male□ 2 years old, 3 years old, 3 years old. Figure 4

Claims (1)

【特許請求の範囲】[Claims] １、炭素を含まないフッ素系ガスを用いて等方性エッチ
ングを行った後に、ハロゲンガスを用いて異方性エッチ
ングを行い半導体基板上の多結晶シリコン膜にテーパ状
の側面をもつパターンを形成することを特徴とする半導
体装置の製造方法。1. After performing isotropic etching using a fluorine-based gas that does not contain carbon, anisotropic etching is performed using halogen gas to form a pattern with tapered side surfaces on the polycrystalline silicon film on the semiconductor substrate. A method for manufacturing a semiconductor device, characterized in that:
JP24619385A 1985-11-05 1985-11-05 Manufacture of semiconductor device Granted JPS62106629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24619385A JPS62106629A (en) 1985-11-05 1985-11-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24619385A JPS62106629A (en) 1985-11-05 1985-11-05 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS62106629A true JPS62106629A (en) 1987-05-18
JPH051978B2 JPH051978B2 (en) 1993-01-11

Family

ID=17144896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24619385A Granted JPS62106629A (en) 1985-11-05 1985-11-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62106629A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0383064A (en) * 1989-07-28 1991-04-09 American Teleph & Telegr Co <Att> Etching of semiconductor device of integrated circuit
US5686363A (en) * 1992-12-05 1997-11-11 Yamaha Corporation Controlled taper etching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0383064A (en) * 1989-07-28 1991-04-09 American Teleph & Telegr Co <Att> Etching of semiconductor device of integrated circuit
US5686363A (en) * 1992-12-05 1997-11-11 Yamaha Corporation Controlled taper etching

Also Published As

Publication number Publication date
JPH051978B2 (en) 1993-01-11

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