JPS60101658A - Memory control system - Google Patents

Abstract

PURPOSE:To attain a dynamic change of each area range by dividing the inside of the same memory into optional areas to use the areas as an area for action of an error detection parity or an area for an error correcting. CONSTITUTION:Memory parts 402 and 404 having at least a 1-bit parity area added are provided to memory parts 401-404. An error correction flag register FF413 gives an indication to the parts 401-404 in an error correction system for writing of data. An error correction write control part 405 controls the data writing to the parts 401-404 by an output 456 of the FF413 in a parity check system or an error correction system. An error correction read part 406 decides the parity check system or the error correction system for output data on parity areas 402 and 404 and controls a parity checker 104, a code checker 304 and a 1-bit error correction part 12. Thus it is possible to write data to an optional area of the memory part in the parity check system or the error correction system.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory control system, and in particular divides the same memory into arbitrary areas, and divides the same memory into arbitrary areas for error detection and error correction.
This invention relates to a memory control method that can be used as an I effect and dynamically change the division range.

[Background of the Invention] Conventionally, data errors in the screen memory, program memory, etc. of video data terminals, for example, have only been detected using a consistency check method.On the other hand, in the terminal controller of the terminal, memory capacity )1 is large, the data is checked using the EC (Error Correction) method. In the EC method, the check bit alone requires a large capacity, and occupies about 37.5% of the total memory capacity. In contrast, in the integrity check method, one check bit is sufficient. Therefore, if the parity check method is used for unimportant memory areas and the EC method is used only for important areas, it is possible to check the normality of memory data while minimizing the increase in the number of memory users.

FIG. 1 is a diagram showing the configuration, memory mapping, and screen display of a general processing system.

In a processing system as shown in FIG.
The bus 107 has a memory (hereinafter referred to as MEM) 101 and a line control device (hereinafter referred to as C).
A) 102, display screen control device (hereinafter referred to as DSPA) 10
3. A keyboard control device (hereinafter referred to as KBA) 104 is connected. In addition, the display device (hereinafter referred to as CR, 1') 105 via the DSPA 103
Keyboard (hereinafter referred to as KBD) 10 via A 104-
6 is connected.

Furthermore, MEMIOI has the memory mapping shown in FIG.
, data area 109, and display screen area 110. Suppose that such a processing system is used in a bank, etc., and the processing shown in the screen shown in Figure C5) is carried out. Screen 105
(in the CRT), when inputting or outputting money, first
``Deposit'' is displayed, !l: ,i Heter Gt''
Enter using 10.000'' KB D 106. Data input from KBD106 <10,000
> is first stored in the M EMl 01 data area 109, and - is also stored in the display screen area 110 at the same time. Data <10,000> in data area 109 is CAl
is sent to the central processing unit (hereinafter referred to as host) via O2,
This is processed as deposit data. On the other hand, the data in the display screen area 110 is displayed on the screen 1051 as operator confirmation data. Similarly, data <1.000> for one withdrawal "9" is stored in the data area 109 and the display screen area 110, and the screen 105 displays "Is the amount correct?" ” is displayed. Therefore, if the operator presses <Y> (
When inputting ``correct'', the CPU 100 performs a predetermined process to extract the data from the data area 10Q of the MEM 101.
*<10,000>,! =<1.000> as CAlO2
It will be sent to the host via. Here, suppose M
If the data in the data area 109 of the E M 101 is incorrect and <10°000> becomes <100.000>, the difference <90,000> will be added incorrectly, causing problems in business, etc. There will be a significant impact on the In order to prevent such so-called "data corruption", in the prior art, a "parity check method" as shown in FIG. 2 and an "ECC method" as shown in FIG. 3 have been implemented. When data corruption occurs, an error message is output so that it can be dealt with. In the example shown in Fig. 2 α), the 8-bit write data 205 is connected to the parity bit generator 203 of the memory 2'01, and the output 206 of the parity bit generator 203 is connected to the parity bit 20.2. There is. On the other hand, the write signal WE200 is input to the memory 201 and the parity bit 202, and the output read data 207 of the memory 201 and the output 208 of the parity bit 202 are input to the parity bit checker 204. or,
The resulting error 209 is parity bit checker 2
It is output from 04.

The operation of the parity check method is well known and will not be described in detail here, but when writing to memory, the parity generator 203 performs exclusive OR on the 8 bits of the write data 205, and the 8 bit data is n of
The number of bits in 111 is calculated, and the output 206 is set to "1" depending on whether it is an odd number (odd parity method) or an even number (even parity method), and the output 206 is also written to the parity bit 202 by the WE 200. On the other hand, when reading the memory, calculate the memory output 20708 bits and the number of 1 bit °°l'' of the parity bit 208. For example, if the odd parity method is used, if the number of 1'' is an odd number, it can be read correctly. If the number is even, at least one of the nine bits is between 0" and °'1" or I
If there is a change from I+ to °"O", the output 209 is generated as an error. Here, we have stated "at least 1 bit", but if we consider the case where an error of 2 bits or more occurs, for example, in the odd parity method, the write data table on the F side in Figure 2 (2) and the write data table in Figure 2 (2) ), the data °'oooooooo" and parity pit"
When the write data 251 of ``1'' is read from memory No. 201 and 202: 8, the data is ``oooo''.

000" and parity bippi I II, it will be normal 2,59. However, the data "0001000"
0” and parity bibbi O11 write data 252,
When reading, the upper bit 255 changes from 0°' to 1'', and the slightest bit of 0°' becomes an error 260, which makes it possible to detect data defects. data will no longer be sent to.

Similarly, for the write data 253, the parity bit 256 changes from "1" to O" k-, and the number of "1°' becomes an even number, so an error 261 occurs. However, read the write data 254 of data '01010101'' and parity bit 1'', and write data 257.
and 258゛°2 bit 1' from OII++ I I
Even if it is converted to I, the number of IT l 11 is odd, so it is treated as normal 262, which is the parity method. H (There was a world.

The EC method shown in Fig. 3 is an improved version of the parity method. In FIG. 3, 8-bit write data 305 enters memory 30] and error correction code generator (error correction hood generator) 303, and as a result, 5-bit output crab 506 is sent to EC pin 302. I'm trying to type. Write signal WB 300
I am connecting memory 01 and EC 302K. (11) On the other hand, the output 307 of the memory 301 is input to the error correction code checker 304 as a 1-bit error lI' 312. Error correcting food checker (error correcting code detector) 304 - &: indicates that the ECC bit output 308 is human input and does not indicate 1 bit error, 1 error 309, and 2 bit error does not indicate 2.
Error 310 is output. Also, at the same time when 1 error/3o9 occurs, the error correction code checker 30
4, the output 311 is subjected to one-bit error correction 312, and read data 313 after the correction is output.

To briefly explain the EC method, 8-bit write data 305 is sent to the error correction code generator 3.
Generates a 5-bit error correction code from 03c,
When a write signal is issued by WB2°O, 8 bits of write data 305 and error correction code 3°6 are generated.
Also writes 5 bits of data to memory. On the other hand, in the case of reading, the memory output 30708 bits and the EC bit output 308 5
The bits are checked by an error correction code checker 304, and it is checked whether the read data is normal according to a certain ff rule, but has a 1-bit error or 2 or more bit errors. Furthermore, if there is a 1-bit error, the error correction code checker 304
Output 311 is issued and 1 bit error correction 312C
The erroneous 1-bit data is returned to normal and output as read data 313.

In this way, the EC system can correct a 1-bit data error and can also report errors of 2 or more bits, so it is effective in increasing the reliability of the memory. In particular, −, large dynamic memory has α
It is known that 1-bit errors are more likely to occur due to r4, and correction of 1-bit errors using F and C method numbers J is also effective. Now, if the EC method is applied to all memory C scales, there will be no need to worry about it, but the EC method has the disadvantage that the memory increase becomes 7JI+. That is, 8
For each bit of data, 5 EC bits, which account for 63% of the data, must be used.

I'm sure that as the number of data bits increases, the proportion decreases.
The number of EC bits t↑1 for this method is large. It also increases the cost of the entire system.

On the other hand, since the parity method requires only one negative phase per 8 bits, the effect on the overall system cost is reduced. Also, like the display screen area 110 in Figure 1, parity pits are not necessarily necessary and there are areas where the impact is small even if the data is incorrect, and there are areas like the data area 109 where the data sent to the post is incorrect. That's why (the mallet also exists.

Therefore, using the same memory system <: z4, external conditions and main rudder 1. From '419' k-, imposed correction (EC) operation and error detection (parity check)
A memory control method was proposed that did not require switching operations (transferred from IPf Publication No. 1983-45266).
.

In the case of the mouth, since the switching signal is connected to the input/output terminal of the memory, only one operation mode exists during system 41 operation. In other words, the operating mode is static. If the memory of the above conventional method is changed to error correction operation mode l-, 7 (, TI, the rod 41M
As shown in (b) (J52 bytes (16 bits) wide data field and 6 bits), the ECC field of 16a is all used. Furthermore, when switching to the error detection 7111 operation mode, as shown in Figure 4(c) K, the 2-byte wide data section is used as is, but only 2 bits of the 6-bit wide area are used as parity. The remaining bits (shaded areas) cannot be used. If there is an area in the memory where data values must not be erroneously set (program area and data area) as shown in Figure 1 (Figure 1), and an area where it will not have much effect even if the data value is changed (display 1).
In the 13th case, which is 11 minutes after 1jfi blood dissemination), the n'i person is made to perform the 11th residence in the error internal type (E C), and the F person is given gI.
! (When attempting to perform the parity detection (parity) movement I/ν, under the conventional system, two memory control units 1.2 are provided as shown in Figure 1(a), and input information is input. For a pair, each control terminal 5, 6 has an error stamp code 1-114.
No. ``!1'', error detection code signal ``L''''
11+(Eru% Sof+''=There is.And this tv・
Even if you set it to 11th mode, it will remain in that 11th mode at least while the power is on.

(Objective of the Invention) An object of the present invention is to solve the first problem by processing an arbitrary memory work area by a single correction operation without adding a memory capacity or a memory control unit. or a memory with high iq characteristics that can be processed by error detection operation Mi! i (4 provides the I11 method.

[Summary of the invention]

In order to achieve the above object, the memory control method of the present invention is as follows:
A parity check method is implemented using a memory section to which at least a 1-bit security area is added, an error correction flag register that instructs data writing to the memory section using an error correction method, and an output of the error correction flag register. Alternatively, an error correction write control section that controls writing of data to the memory section using an error correction method, and the data read out from the content C of the security area of the memory using a security check method or an error correction method. The present invention is characterized in that it includes an error correction read control section that determines whether the parity checker or code checker and the 1-bit delta correction section are correct.

[Embodiments of the invention]

FIG. 5 is a diagram illustrating the principle of instant production of the present invention.

In the present invention, the same memory is divided into arbitrary areas as shown in FIG.
It can be used for either parity (parity) operation or error correction (EC) operation, and the range of each area can be dynamically changed. That is, a flag flip-flop is provided for writing, and it is made to correspond to a check bit, and the operation mode is selected by turning on/off the flag.
The operating mode is switched by checking the check bits independently of the flip-flop. In Fig. 5(b), at least 2 bytes of memory are arranged in the word direction, and each byte has 1 bit of flag memory C), 8 bits of data bits in the word, and 1 bit of parity bit, and can be set by a program. For EC type memory writing, a 1-bit register is provided. When the program accesses the memory using the EC method, after setting the register to °゛l'',
The memory control unit 3 inputs 1 into the memory using the EC method.

In that case, one byte of the word is data,
Write 5 bits of the other bytes as EC bits. At the same time, set the memory flag bit (F) to 11. When there is a memory read request, the memory control unit 3 reads data from the memory in word units, recognizes that if the flag bit (F) is °l'', it is l-J, EC method, and reads one byte of the word. is used as data, and other bytes are used as EC bits to check for errors and temporarily view data for 1-bit errors.Also, if the register is "0'"
7 lag pins of memory)
When (F) is 0'', memory read function, parity
Create a rabbit as a check method. In the parity check method, data (8 bits) and parity bit (1 bit) are written in each byte of a word.

In Figure 5(C), one data (8
In the parity check method, data is written, read, and output independently for each address, but in the EC method, there are two
Set the addresses as one set, write data (8 bits) to the first address, and write the EC bit (5 bits) to the second address. +2 to 1, n+ n″a, and 2 address;
1! A function for continuous access is required. Figure 5(b) (
In any case of Q), an arbitrary number of operation modes exist in an arbitrary area during system operation, and two flij single operation modes ('I
I can change.

Next, a specific example of the method of Fue 5 (Fig. 5) will be shown.

FIG. 6 is a block diagram of a memory control unit and memory showing an embodiment of the present invention, and FIG. The figure is an operation flowchart of the 'write b program to the memory using the EC method in figure 6.

In FIG. 6, 8-bit write data 450 is input to a memory 401, a parity generator 103, an error correction code generator 303, and a selector 407. Output 45 of parity generator 103
8 is connected to selectors 408 and 409, and a 5-bit output 459 of error correction code generator 303 is fy-connected to selector 407. FCC flag
Output 456 of flip-flop 413 and write signal WE
+51 and the lowest address A O signal 452 are input to the EC write control unit 405, and the output is the memory 403 and 4.
A W E O-453 that instructs writing of 04 and a WE1 signal 454 that instructs writing of memories 401 and 402 are connected to each memory, and the parity generator 1
03 output 458 selection instruction signal select I) P 4
57 is being input to selectors 408 and 409. The output 460 of the selector 407 is stored in the memory 403 as the selector!
The output 461 of 08 is input to memory +04, and the output 62 of selector 409 is input to memory 402, and is used as write data. The 8-bit output 467 of memory 401 is
Selector 410 and error correction code checker 30
The 8-bit output +64 of the memory 403 is connected to the selector 410, and the lower 5-bit output 463 of the memory 403 is connected to the error correction code checker 304.
It is connected to the. Output (PIB) 46 of memory 402
8 is input to the selector 411 and the EC read control unit 406, and the output (PIA) 469 of the memory 402 and the memory 4
04 output (POA) 466 and lower address AO signal 4
52 is also connected to the EC read control unit 406.The output (POB) 465 of the memory 404 is connected to the EC read control unit 4.
06 and selector 411 are input.

Check parity output 472 of EC read control unit 406
The parity checker 104 k-instructs a parity check, and the output 481 indicates an abnormality in the matching of the two pins of the memories 402 and 404 as a fourth error, and the check E C output 470 is connected to the error correction code checker 304 and E Ck
The select H output 471 is connected to the selector 410 and instructs the selection of data in the memory 401 (IIit), and the data through output 473 is input to the 1-bit error correction/data through 412 to select the data. The output 475 of the selector 411 is output as a parity bit, and the 8-bit output 474 of the selector 410 is output as data.
It is input to the parity checker 104 and causes a third error to be generated at the output 480 when an error occurs. The 8-bit output 474 of the selector 410 is connected to the 1-bit error correction/data through 412, and in response to the data correction request of the output +78 of the error correction code checker 304, the 1-bit error temporary data is corrected, and the corrected data is sent to the output 479. In response to the data through request of the ECC read control hand 06 output 473, the output 479 is generated without modifying the memory read data.The selector 411 contains the lower address AO signal 452, and the AO The double signals "'1" and "O"' cause the output 468 of the memory 402 and the output 4 of the memory 404 to
65 is being switched.

The error correction code checker 304 outputs a first error 477 indicating the occurrence of a 1-bit error and a second error 476 indicating the occurrence of a 2-bit error. In addition,
When the output 457 of the EC light control unit 405 is °'0', the selectors 408 and 409 select 'lO' and '11, respectively.
” and produce these at outputs 461 and 462.

FIGS. 7(a) and 7(b) show the EC light control section 4 of FIG.
4 is a gate diagram of the 0 convex and the EC read control section 406. FIG.

In the write control section of FIG. 7(-), the interrupt signal WE
451 is input to the AND gates 501 and 503, the lowest address AU signal 52 is input to the OR gate 502 and the inverter 505, and the output 456 of the 1C flag flip-flop 413 is input to the other inputs of the OR gate 502 and the OR gate. 504 and an inverter 506. The output 507 of the OR gate 502 is the AND gate 501
, and a WE1 signal 454 is output. The output 509 of the inverter 505 is input to the OR gate 504.
The OR output 508 is input to the AND gate 503 and the WEO signal 453 is output. On the other hand, inverter 50
6 is a selection instruction signal select DP457.

FIG. 7(b) In the read control unit 406k-, the output (PIA) 469 of the memory 402 is inputted to the inverter 551 and the AND gate 557, and the output (PIA) of the memory 40i is
OA) 466 is inverter 553 and AND gate 559
The output (PIB) 468 of the memory 402 is input to the AND gate 557, and the output (PIB) of the memory 404 is input to the AND gate 557.
OB) 465 is input to the inverter 560 km, and the lower address AO signal 452 is input to the AND gate 554. The output 563 of the inverter convex 51 and the output 564 of the inverter 553 are input to the AND gate 552,
Its output 472 (check parity) is internally connected to AND gate 554 and OR gate 561.

Output of AND gate 554, 565 is OR gate 556
and its output becomes 71 (select 1()).

The output 568 of the inverter 560 is input to an AND gate 559, and its output 567 is input to an AND gate 558 and an EXOR gate 562. The output 566 of AND gate 557 is connected to AND gate 558 and I! : X Ott is input to the gate 62, and the output 470 (check EC) of the AND gate 558 is internally input to the O'γ gate 556, EXOIt
Output 481 (fourth error) of gate 562 is internally -
(or game) 561, and becomes its output 473 (data through).

Based on the connections shown above, the operation of this embodiment will now be described.

With reference to FIGS. 6 and 8, a case will be described in which data is written to the memory in the EC mode. When writing data in the EC mode, processing can be performed according to the flow shown in FIG. The determination unit 601 checks whether the mode is EC mode,
In the EC mode, the execution unit 602 executes F/F (413'
). In FIG. 6, the EC flag flip-flop (ECFLG F/F) 413 is "l" I
- When this is set, the output 456 becomes "1" and is transmitted to the EC light control section 405. Next, when the execution unit 603 writes to the memory, the 8-bit write data 450 becomes a specific value, and the write signal W
E 451 becomes °°1”. EC light control unit 405
At 405 in FIG. 7(a), the write signal WE4
When 51 becomes 1", 2 of AND gates 501 and 503
One side of the human power becomes “l + t,” and each or gate 501
and waits for output from 504.

On the other hand, since ECFL'G F/F 413 is set to 1", the inputs of OR gates 502 and 504 are "]", and the outputs of OR gates 502 and 50 are also "1".
Then, the two input conditions of the AND gates 501 and 502 are aligned, and the WEI indicating writing to memories 401 and 402 is from the output 454 of 501, and the WEO indicating writing to memories 403 and 404 is input to the AND gate. 503, respectively. Also, E
Output 456 of CFLG F/F413 is inverter 50
Since it is also included in 0, its output (select) DP) 4
57 is inverted and becomes "0", and selectors 408 and 40
9 selects the output 458 of the parity generator 103, the selector 409 selects 111'', and the selector 408 selects ``10''.Similarly, selector DP457 [ma selector 407 & Therefore, the 5-bit output 459 of the error correction code generator 303 is selected instead of the 8-bit write data 450. In this selection state, the write signal WB451 becomes pulse-like. , the memory 401 will write the write data 450, the memory 402 will write the 11" data, the memory 403 will write the EC code, and the memory 404 will write the 10" data. Of the 8 bits in the memory 403, , only the upper or lower δ bits are written with the ECC code, but the remaining 3 bits are used exclusively for memory read f, (therefore, there is no need to write a specific data value. When writing to the memory is completed, the execution unit 604 As shown in , the F/F (413) is reset, and the process ends.

Next, a case will be described in which the memory data written as described above is read.

When a memory read request is made, memories 401, 402, 403, and 404 are read out in FIG. 6. At this time, outputs 469 (PIA) and 468 (
PIB) is “11′, and the output 466 of the memory 404
When CPOA) and 465 (POB) are “lO”, the ECC read control unit 406 to which the above signal is input
It is recognized that the memory is written in F and C modes. That is, at 406 & in FIG. 7(b), P I
Since A469 and PIB468 are °゛]'', the input conditions of the AND gate 557 are aligned, and the output 566 becomes ``1'', while POA4 (3 (3 is °°1'', P
Since OB465 is 0'', the human power conditions for AND gate 559 are met, its output 557 becomes 1'', and the input conditions for AND gate 558 are met.

Therefore, the output 470 of the AND gate 558 becomes "1'" and is sent out as a check IEC, and at the same time it is also ORed to the 1 OR gate 556, and the output 471 is sent to the select F ((data on the memory 401 side is selected by the selector 410). On the other hand, E
Since the input of the XOR gate 562 is °'oo", its output (fourth error) 481 is OIT. Also, the inputs of the AND gate 552 and OR gate 561 are both 00'", so its output check parity 470 and data through 4
73 becomes OIT, and neither a parity check instruction nor a data through instruction is issued. Therefore, the selector 410 selects the 8-bit output of the memory 401, and the output 474
The data is sent to the 1-bit error correction/data through 412 as a 1-bit error correction/data through 412. On the other hand, error correction code checker 3' 0
4 is the 8-bit output signal 67 of the memory 401 and the memory 40.
Input 5-bit output 463 of 3, 1-bit error/2
Detect bit errors. Here, when a 1-bit error occurs, when the 1-bit error 477 becomes ``I11'', the output data correction 478 of the C error correct code checker 304 becomes 11'', and the 1-bit error correction/data through 412 is transmitted. , the error pits are corrected and the read data 479 is output as correct data. If a 2-bit error occurs, the second error 476 will be 1", but the data will not be corrected. Also, if there is no error, the 8-bit output 467 of the memory 401 will be in the read data +79. It can only be conveyed as is.

Next, we will explain one case in which data is written to memory in parity mode.

In the parity mode, in the processing flow of FIG.
The memory write of the execution unit 6.3 is executed without executing the set of . Therefore, in the EC write control FfS 405, the lowest address AO signal 452
f) “l”, 0″w, or gate 50
2, or 504 (7) dochirakat-” 1” k-t
Le.

For example, if the AO signal 452 is °°o', the input of the OR gate 504 is °°l', and the ant game) 50
3, the write signal WE451 is ANDed, and the memory 4
03.Write signal (WEO) 453 to 404 is N I
Becomes I+.

On the other hand, memo! Write signal to J401, 402 (WEl
)454 is 0'', select DP457 is °゛1
”. Therefore, the data to the memory 404 is sent to the output 4 of the parity generator 103 by the selector 408.
58 is selected and inputted as its output 461, and furthermore, the data to the memory 403 is selected by the selector 407, and is input as the output 461.
Bit write data 450 is selected and its output 46
Entered as 0. At this time, write signal WE4δl
When is transmitted in the form of a pulse, only the write signal (VBQ) is output, and the memory 403 writes the 8-bit write data 450, and the memory 404 writes the parity bit.

Since the memory 404 has 2 bits, the bits other than the bits assigned as parity pits must be written with 0. For example, writing to memories 401 and 402 is performed.

Next, memory read in parity mode will be explained.

When there is a memory read request, the memories 401, 402, 403, and 404 are read in FIG. 6. At this time, outputs 469 (PIA) and 468 (
P113) is °'OX" (X is a parity pit and "l'
' or °'0'), and the outputs 466 (POA) and 465 (PUB) of the memory 404 are °'OX
”, the EC read control unit 406 to which the above signal is input recognizes that the memory is being written in parity mode.

That is, at 406 in FIG. 7(b), since PIA 459 and POA 466 are both N011, the AND condition of AND gate 5.52 is established through inverters 551 and 553, and the output 472 (check parity)
It is output. Therefore, in the AND gate 554, when the lowest address AO signal 452 is "do", its output 565 becomes 1°2, and its output 471 (select) H) is outputted through the OR gate 556.On the other hand, the PI
Since A469 and POA 466 are 'O''T, the AND condition of 7nt J+') 557 and 559 is not satisfied, and the AND condition of Antogame) 5.58 and EX OR game) 562 is ``O''.
” is t! Also, the check parity 472 is 1”
Therefore, OR gate 561 is connected and data through 4
73 is output. As described above, the operation of the EC read control section 406 in FIG. 6 is as follows. When the selector 410 selector 410 selects the lower address AO signal v 452 ``1°'', the memory 4
This signal selects the 8-bit output data 467 of 01,
When the AO signal 452 is "o", the 8-bit output data 46 in the memory 403 is selected.On the other hand, when the Ao signal 452 is "1", the P of the mailer U 402 is selected by the selector 411.
When IB468 is '0', POB of mail-v-9404
Select 465 respectively. The 8-bit data 474 and 1-bit parity signal 475 selected in this way are
A parity check is performed based on the input to the parity checker 104 and the output 472 (check parity) of the EC read control unit 406, and if there is an error, a third error 480 is generated.

On the other hand, the 8-bit data 4 selected by the selector 410
744t, it is input to the 1-bit error correction/data through 412, but since the data through signal 473 is "l I+", it is transmitted as is to the output 479 and becomes read data.

FIG. 9 is a block diagram of a memory control section showing another embodiment of the present invention. In FIG. 9, an error correction code generator & checker (ECGC) 702 is provided to generate an EC code when writing to memory.
This is shared as a checker when reading memory. The 8-bit data to the ECGC 702 is sent to the selector 70.
1, it is blocked by the write mode signal 703, and the output cuff 04 is EC'GC702G: Great sword. When writing to memory, the 8-bit write data 450 is input to the ECGC 702 through the selector 701 according to the write mode signal 703, and the 5-bit output 459 is obtained. At this time, the 8-bit memory data 467 is outputted to the output cuff 04 through the selector 701 according to the write mode signal 703 NOIJ, and checked together with the 5-bit EC code 463.

Furthermore, as another embodiment of the present invention, the data width in one memory read/write was set to 16 data bits and 4 parity bits, but it was changed to 8 data bits and 2 parity bits, and in the EC mode, the write data Even if the writing and the writing of the EC code are carried out twice, the effect is the same.

However, in this case, since the memory cycle is performed twice, there is a drawback that the memory processing time increases.

In the present invention, when the memory control section is configured with an IC or the like, the amount of hardware required is the same as the parity check method and the EC method combined, which is larger than the conventional method, but the LS
By converting it into an integrated circuit, the memory and memory control unit can be made smaller and lower in cost.

〔Effect of the invention〕

As explained above, the present invention merely increases the number of memory bits by at least 1 bit for every 8 bits of data and 1 bit of parity pit. Since the region can be processed by error correction operation or error detection operation, it is possible to improve the processing capacity of the information processing system.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration, memory mapping, and screen display of a general information processing system, Figure 2 is a diagram showing the memory surroundings and data table of the conventional parity check method, and Figure 3 is a diagram of the conventional EC method. Figure 4 is a diagram showing the memory periphery, Figure 4 is an explanatory diagram of the conventional switching type memory control system, Figure 5 is a diagram showing the operating principle of the memory control system of the present invention, and Figure 6 is an example of the present invention Ihb. FIG. 7 is a logic gate diagram of the EC write control section and EC read control section in FIG. 6, FIG. 8 is a flowchart of memory write processing in the present invention, and FIG. FIG. 3 is a configuration diagram of a memory peripheral section showing another embodiment of the invention. 1.2, 3: Measuring control section, 201, 202° 301.
302, 401-404: Memo +), 4゜5=EC
Light control unit, 406: E CIJ-)” control unit, cow 13: EC flag flip-flop, 303:
Error correction code generator, 103: Parity generator, lo4: Parity checker, 304:
Error correction code checker. IN 4 Figure (b) (c)

Claims (1)

[Claims] (1) At least one
A memory section with a bit parity area added, an error correction flag register that instructs data writing to the memory section using an error correction method, and an output of the error correction flag register to perform a parity check method or an error correction method. The error correction write control unit controls the writing of data to the memory unit, and the content of the parity area of the memory determines whether the data to be read is of the parity check type or the error correction type, and the data is written in the F memory. It has an error correction read control section that controls the parity checker, code checker, and 1-bit error correction section, and writes data to any area of the above memory section using either the parity check method or the error correction method. A memory control method characterized by: