JPS5999752A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS5999752A JPS5999752A JP20896882A JP20896882A JPS5999752A JP S5999752 A JPS5999752 A JP S5999752A JP 20896882 A JP20896882 A JP 20896882A JP 20896882 A JP20896882 A JP 20896882A JP S5999752 A JPS5999752 A JP S5999752A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- substrate
- cover
- chip
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
「発明の技術分野」
本発明は半導体集積回路素子（以下ＩＣチップという）
等の、集積回路素子を基板に配置してなる混、成業積回
路装置の改良に関する。 １［発明の技術的背
景］
従来、混成集積回路装置としては、第１図〜第５図に示
すものが知られている。[Detailed Description of the Invention] "Technical Field of the Invention" The present invention relates to a semiconductor integrated circuit element (hereinafter referred to as an IC chip).
The present invention relates to improvements in hybrid integrated circuit devices in which integrated circuit elements are arranged on a substrate. 1 [Technical Background of the Invention] Conventionally, hybrid integrated circuit devices shown in FIGS. 1 to 5 are known.
第１図に示す混成集積回路装置は、基板１上にＩＣチッ
プ３を接着剤２によって止着するとともに、基板１に形
成された回路パターンの電極４とＩＣチップ３の電極間
をボンディングワイヤ５によって接続してなるものであ
り１．第２図に示すものは基板１の電極４ノ〕１ら延る
ビームリード６を介してＩＣチップ３を取付けたもので
ある。In the hybrid integrated circuit device shown in FIG. 1, an IC chip 3 is fixed onto a substrate 1 with an adhesive 2, and a bonding wire 5 is connected between an electrode 4 of a circuit pattern formed on the substrate 1 and an electrode of the IC chip 3. It is connected by 1. In the device shown in FIG. 2, an IC chip 3 is attached via a beam lead 6 extending from the electrode 4 of the substrate 1.
また、第３図に示すものは、基板１に止着されたＩＣチ
ップ３と、基板１上の電４４λ４間を端子リード、７に
よって接続したものであり、第４図に示すものは、ＩＣ
デツプ３をセラミックチップキレリヤ８に形成した四部
９に止着し、このセラミックチップキ、ヤリＡ７．８□
に形成した電極とＩＣチップ３とをボンディングワイヤ
５によって接続するとともに、・このセラミックチップ
キ・ヤリャ８を基板１の電極４上に重ねて半田１０によ
って接続してなるもので□ある。 □ ・
さらに、第５図に承り混成集積回路装置は、基板１の電
極４に、半田バンプ１１を取イ；１けたＩＣチップ３を
重ね、その半田バンプ１１を溶かすことによって電イ水
４と接続しでなるものＣ′ある。In addition, the one shown in FIG. 3 is one in which the IC chip 3 fixed to the substrate 1 and the electric wire 44λ4 on the substrate 1 are connected by a terminal lead 7, and the one shown in FIG.
The depth 3 is fixed to the fourth part 9 formed on the ceramic chip rear 8, and the ceramic chip
The electrodes formed on the substrate 1 and the IC chip 3 are connected by bonding wires 5, and the ceramic chip carrier 8 is stacked on the electrodes 4 of the substrate 1 and connected by solder 10. □ ・Furthermore, the hybrid integrated circuit device shown in FIG. There is a connection C'.
［背崇技術の問題点１
しかしながら、上述の第１図〜第４図に示−リ′混成東
積回路装置にあっては、ＩＣデツプ３と基板１の電極４
との接続がボンディングワイヤ５、ビームリード６、端
子１）−ドアおよびセラミックチップキャリヤ８等を介
して行なわれているので、ＩＣチップ３と電極４間の接
続に要するスベ〜スかＩＣチップ３よりも大幅に広くな
って、ＩＣチップ３の高密度実装化が回動となる欠点か
ある。[Problem 1 in the transgressive technology] However, in the hybrid Toshiba circuit device shown in FIGS. 1 to 4, the IC depth 3 and the electrode 4 of the substrate
The connection between the IC chip 3 and the electrode 4 is made via the bonding wire 5, beam lead 6, terminal 1)-door, ceramic chip carrier 8, etc. This has the drawback that the IC chip 3 has to be rotated when mounted in a high density.
また、第５図に示す混成集積回路装置にあって（よ、Ｉ
ｃチップ３に予め半田バンプ１１を取付けなければなら
ず、ＩＣチップ３の下面の半ば１バンブ１１ど電極４と
の正確な接続が煩雑であるので、製造組立能率が低く、
コスト高となり易い欠点かある。Furthermore, in the hybrid integrated circuit device shown in FIG.
It is necessary to attach the solder bumps 11 to the c-chip 3 in advance, and it is complicated to accurately connect the bumps 11 on the lower surface of the IC chip 3 to the electrodes 4, resulting in low manufacturing and assembly efficiency.
The drawback is that it tends to be expensive.
［発明の１］的」
本発明はこのような従来の欠点を解決するためにな５れ
たもので、混成集積回路装置にあって基板に保護カバー
を被せる点に着目し、高密度化、放熱効果および組立能
率の良好な混成集積回路装置の提供を目的とする。[First aspect of the invention] The present invention was developed to solve these conventional drawbacks, and focuses on the point of covering the board with a protective cover in a hybrid integrated circuit device. The object of the present invention is to provide a hybrid integrated circuit device with good heat dissipation effect and assembly efficiency.
Ｕ発明の概要」
リーなわら本発明は、基板に電極を形成し、この基板を
覆うカバーの内面に集積回路素子を止着ツるとともに、
この止着された集積回路素子の゛電極をそのＢ 扱の電
極に圧接させるようにしてそのカバーを」二記基板に被
せＣなることを特徴とブる。SUMMARY OF THE INVENTION The present invention forms an electrode on a substrate, fixes an integrated circuit element to the inner surface of a cover that covers the substrate, and
The feature is that the electrode of the fixed integrated circuit element is brought into pressure contact with the electrode B, and the cover is placed over the substrate C.
［発明の実施例ｊ 以下不発明の詳細を図面を参照して説明する。[Embodiment of the invention j The details of the invention will be explained below with reference to the drawings.
なお従来例と共通する部分には同一の符号を付す。Note that parts common to the conventional example are given the same reference numerals.
第６図は本発明の混成集積回路装置の一実施例を示す断
面図である。基板としての多層配線基板１は、その表面
に複数の電極４が形成されている。FIG. 6 is a sectional view showing an embodiment of the hybrid integrated circuit device of the present invention. A multilayer wiring board 1 serving as a substrate has a plurality of electrodes 4 formed on its surface.
この電極４には金ペースト等によって接続ピン１２か形
成己れている。この接続ビン１２は金ペース１へに限ら
ず一般的な導電性の接着剤や導電体を用いることも可能
である。A connecting pin 12 is formed on this electrode 4 using gold paste or the like. The connection pin 12 is not limited to the gold paste 1, but can also be made of a general conductive adhesive or conductor.
この多層配線基板１には、絶縁シート１３に導電層１４
を止着した２層構造のカバー１５が、導電層１４を内側
にしてその導電層１４を多層配線基板１の端縁近くの電
極４に接続するように被せられている。This multilayer wiring board 1 includes an insulating sheet 13 and a conductive layer 14.
A cover 15 having a two-layer structure with a conductive layer 14 fixed thereon is placed over the multilayer wiring board 1 so that the conductive layer 14 is connected to the electrode 4 near the edge of the multilayer wiring board 1.
また、カバー１５の導電層１４すなわち内面には導電性
エポギシ樹脂からなる接着剤１６が塗イｂ３れ、この導
電性接着剤１６を介してＩＣチップ３が導電層１４に止
着されており、このＩＣチップ３はその外部接続電極１
７を接続ビン１２の先端に圧接されている。Further, the conductive layer 14 of the cover 15, that is, the inner surface, is coated with an adhesive 16 made of conductive epoxy resin, and the IC chip 3 is fixedly attached to the conductive layer 14 via the conductive adhesive 16. This IC chip 3 has its external connection electrode 1
7 is pressed against the tip of the connecting bottle 12.
すなわちＩＣチップ３は、カバー１５に止着されるとと
もに、カバー１５を被せた場合、多層配線基板１の電極
４に形成された接続ピン１２にＩＣチップ３の下面に位
置する外部出力電極１７を圧接接続するようになってい
る。なおＩＣチップ３のバイＡ７ス電極く図示せず）や
アース電極（図示省略）＠が導電性接着剤１６に接続さ
れ、導電層１４を介して多層配線基板１の例えばアース
側電極４に接続されている。That is, the IC chip 3 is fixed to the cover 15, and when the cover 15 is covered, the external output electrode 17 located on the lower surface of the IC chip 3 is connected to the connection pin 12 formed on the electrode 4 of the multilayer wiring board 1. It is designed to be connected by pressure welding. Note that the bias electrode (not shown) and the ground electrode (not shown) of the IC chip 3 are connected to a conductive adhesive 16, and connected to, for example, the ground side electrode 4 of the multilayer wiring board 1 via the conductive layer 14. has been done.
このように構成した本発明の混成集積回路装置は、ＩＣ
デツプ３をカバー１５に止着りるとともに、カバー１５
を多層配線基板１に被せるだけでＩＣチップ３の面積内
においてＩＣデツプ３の外部接続電極１７を多層配線基
板１の電極４へ接続可能となり、高密度実装化を図るこ
とが極めて容易となる。またカバー１５は多層配線基板
１に正確に位置決めして被せることが可能であり、ＩＣ
チップ３の正確な位置決めも容易である。The hybrid integrated circuit device of the present invention configured in this way has an IC
While fixing the depth 3 to the cover 15, the cover 15
By simply covering the multilayer wiring board 1, the external connection electrodes 17 of the IC deep 3 can be connected to the electrodes 4 of the multilayer wiring board 1 within the area of the IC chip 3, making it extremely easy to achieve high-density packaging. In addition, the cover 15 can be accurately positioned and placed over the multilayer wiring board 1, and the IC
Accurate positioning of the chip 3 is also easy.
しかも、Ｉｃデツプ３はカバー１５に止着されているの
で、ＩＣデツプ３の発熱による熱が容易に発散し易いの
で、放熱効果も良好となってＩＣチップ３の動作か安定
する。Moreover, since the IC depth 3 is fixed to the cover 15, the heat generated by the IC depth 3 can be easily dissipated, so that the heat dissipation effect is good and the operation of the IC chip 3 is stable.
次に本発明の混成集積回路装置の製造方法の実施例を説
明する。Next, an embodiment of the method for manufacturing a hybrid integrated circuit device of the present invention will be described.
第７図〜第１０図は本発明の混成集積回路装置の一実施
例を示す工程図である。7 to 10 are process diagrams showing one embodiment of the hybrid integrated circuit device of the present invention.
まず第７図に示すように所定の電極４を有する配線パタ
ーンを備えた多層配線基板１を用意する。First, as shown in FIG. 7, a multilayer wiring board 1 having a wiring pattern having predetermined electrodes 4 is prepared.
そしＣ，第８図に示すように多層配線基板′１の電（浜
４に金ペースト等によって接続ビン１２を形成づる。Then, as shown in FIG. 8, connection pins 12 are formed on the wires 4 of the multilayer wiring board '1 using gold paste or the like.
１５’ Ｍ片面に導電層１４を形成した絶縁シート１３
からなるカバー１５の内面すなわちｊ臀達する多層配線
基板に対向する面に導電性エポキシ樹脂からなる接着剤
１６を塗布してＩＣチップ３を止着するく第９図）。15'M Insulating sheet 13 with conductive layer 14 formed on one side
An adhesive 16 made of conductive epoxy resin is applied to the inner surface of the cover 15, that is, the surface facing the multilayer wiring board, to fix the IC chip 3 (FIG. 9).
そして、第１０図に示すように、このカバー１５に１Ｆ
看されたＩＣデツプ３の外部出力電極１７を多層配線基
板１の接続ビン１２に圧接１′るようにして多層配線基
板１に被せ、上述の第６図に示すような混成集積回路装
置が完成する。Then, as shown in FIG. 10, this cover 15 is
The external output electrode 17 of the IC deep 3 that has been checked is pressed 1' to the connecting pin 12 of the multilayer wiring board 1 and placed over the multilayer wiring board 1, thereby completing the hybrid integrated circuit device as shown in FIG. 6 above. do.
なお、本発明の混成集積回路装置の実施にあたっては、
上述の多層配線基板１に限らず、一般的なハイブリッド
ＩＣ用の基板において６実施可能であり、多層配線基板
１の接続ビン１２としても金ペース！・の他、銀ペース
ト等形成が容易で耐食性に優れ導電性の良好な材料を選
択することが可能である。もつともこの接続、ビン１２
は必ずしも必要なものではなく、ＩＣチップ３の外部出
力電極１７が多層配線基板１の所定の電極４へ圧接可能
で′あるな□らば省略することが可能であるが、接続ビ
ン１２を設けるこ左により電極どうしの接続りく確実か
つ薗単になる。In addition, in implementing the hybrid integrated circuit device of the present invention,
Not only the multilayer wiring board 1 described above, but also a general hybrid IC board can be used. Gold paste can also be used as the connection bin 12 of the multilayer wiring board 1. In addition to this, it is possible to select materials such as silver paste that are easy to form, have excellent corrosion resistance, and have good conductivity. Originally this connection, Bin 12
is not necessarily necessary, and can be omitted if the external output electrode 17 of the IC chip 3 can be pressure-contacted to a predetermined electrode 4 of the multilayer wiring board 1, but the connection pin 12 is provided. This makes the connection between the electrodes more reliable and simple.
それにまたカバー１５としては、導電層１４を必ずしも
必要どするものではなく、導電層１４を形成し一’Ｃ’
Ｉ Ｃデツプ３を導電性の接着剤１６で止着することに
□より、ＩＣデツプ３の熱発散を効果的（（行なうこと
が可能なるばかりか、ＩＣチップ、３のバイヤス電極も
しくはアース電ｔ〜等としで利用することか可能である
。In addition, the cover 15 does not necessarily require the conductive layer 14, and the conductive layer 14 may be formed.
By fixing the IC depth 3 with a conductive adhesive 16, it is not only possible to effectively dissipate heat from the IC depth 3, but also to connect the IC chip, the bias electrode 3, or the ground voltage It is possible to use it as ... etc.
また、本発明の混成集積回路装置は、上述のＩＣチップ
３に限らず一般的な集積回路素子を用いる装置において
実施可能であることはいうまでもない。Furthermore, it goes without saying that the hybrid integrated circuit device of the present invention can be implemented not only in the above-mentioned IC chip 3 but also in devices using general integrated circuit elements.
［発明の効果コ
以上説明した。ように本発明の混成集積回路装置は、基
板を覆・、う□、）Ｊ＜＼−の内面に集積回路素子を止
着し、こめ集積回路素子の電極を上記基板の電極に圧接
させるようにし゛Ｃ上記カバーを上記基板に被せてなる
ので、集積回路素子の面積内で基板の電極との接続が可
能となり、集積り路素子の実装面積の高密度化を図るこ
とかできる。[The effects of the invention have been explained above. Thus, the hybrid integrated circuit device of the present invention covers a substrate, fixes an integrated circuit element to the inner surface of )J<\-, and presses the electrodes of the integrated circuit element to the electrodes of the substrate. Since the cover is placed over the substrate, connection with the electrodes of the substrate can be made within the area of the integrated circuit element, and the mounting area of the integrated circuit element can be increased in density.
また、集積回路素子がカバーに止着されるので、放熱性
も良好となって、混成集積回路装置の動作′□の安定化
や動作速度の向土を確保することができ□
る。In addition, since the integrated circuit element is fixed to the cover, heat dissipation is also improved, making it possible to stabilize the operation of the hybrid integrated circuit device and to ensure a suitable operating speed.
第１図〜第５図は従来の混成集積回路装置を示す断面図
、第６図は本発明の混成集積回路装置の一実施例を示ず
断面図、第７図〜第１６′図は本発明の混成集積回路装
置の製造方法の実ＷＡ１例を示す工程断面図である。
１・・・・・・・・・・・・基板（多層配線基板）２．
１６・・・接着剤
３・・・・・・・・・・・・集積回路素子（’ＩＣチツ
デツプ、１７・・・電 極
５・・・・・・・・・・・・ボンディングワイヤ
、′：□
１２・・・・・・・・・・・・接続ビン
□１４・・・・・・・・・・・・導゛電層１５・・・・
・・・・・・・・カバー
代理人弁理士 須 山 佐 −
： 。
１□１1 to 5 are sectional views showing a conventional hybrid integrated circuit device, FIG. 6 is a sectional view showing an embodiment of the hybrid integrated circuit device of the present invention, and FIGS. 7 to 16' are sectional views showing the present invention. FIG. 3 is a process cross-sectional view showing an example of an actual WA method of the method for manufacturing a hybrid integrated circuit device of the invention. 1......Substrate (multilayer wiring board)2.
16...Adhesive 3......Integrated circuit element (IC chip, 17...Electrode 5...Bonding wire
,′:□ 12・・・・・・・・・Connection bin
□14... Conductive layer 15...
・・・・・・・・・Cover agent Sasa Suyama −: . 1□1
Claims (1)
内面に集積回路素子を止着するとともに、この止着され
た集積回路素子の電極を前記基板の電極に圧接させるよ
うにして前記カバーを前記基板に被せてなることを特徴
とする混成集積回路装置。 （２）集積回路素子の電極が、基板の電極に設けられた
接続ビンに圧接されてなることを特徴とする特許請求の
範囲第１項記載の混成集積回路装置。 ” （３）集積回路素子がカバーの内面に形成され
た導電層に電気的に接続された状態で止着８゛れでなる
ことを特徴とする特許請、求の範囲第１項もしくは第２
項記載の混成集積回路装置。[Claims] <1) An electrode is formed on a substrate, an integrated circuit element is fixed to the inner surface of a cover that covers the substrate, and the electrode of the fixed integrated circuit element is attached to the electrode of the substrate. A hybrid integrated circuit device, characterized in that the cover is placed over the substrate in a pressure-contact manner. (2) The hybrid integrated circuit device according to claim 1, wherein the electrodes of the integrated circuit elements are pressed into contact with connection pins provided on the electrodes of the substrate. (3) Claim 1 or 2, characterized in that the integrated circuit element is fixedly attached to the conductive layer formed on the inner surface of the cover while being electrically connected to the conductive layer formed on the inner surface of the cover.
The hybrid integrated circuit device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20896882A JPS5999752A (en) | 1982-11-29 | 1982-11-29 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20896882A JPS5999752A (en) | 1982-11-29 | 1982-11-29 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999752A true JPS5999752A (en) | 1984-06-08 |
Family
ID=16565138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20896882A Pending JPS5999752A (en) | 1982-11-29 | 1982-11-29 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999752A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03112969U (en) * | 1990-03-02 | 1991-11-19 | ||
| EP0685878A3 (en) * | 1994-04-28 | 1996-11-06 | Fujitsu Ltd | Semiconductor package and method of forming the same. |
| US6347037B2 (en) | 1994-04-28 | 2002-02-12 | Fujitsu Limited | Semiconductor device and method of forming the same |
-
1982
- 1982-11-29 JP JP20896882A patent/JPS5999752A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03112969U (en) * | 1990-03-02 | 1991-11-19 | ||
| EP0685878A3 (en) * | 1994-04-28 | 1996-11-06 | Fujitsu Ltd | Semiconductor package and method of forming the same. |
| EP0915504A1 (en) * | 1994-04-28 | 1999-05-12 | Fujitsu Limited | Semiconductor package and method of forming the same |
| US5978222A (en) * | 1994-04-28 | 1999-11-02 | Fujitsu Limited | Semiconductor device and assembly board having through-holes filled with filling core |
| US6088233A (en) * | 1994-04-28 | 2000-07-11 | Fujitsu Limited | Semiconductor device and assembly board having through-holes filled with filling core |
| US6184133B1 (en) | 1994-04-28 | 2001-02-06 | Fujitsu Limited | Method of forming an assembly board with insulator filled through holes |
| US6347037B2 (en) | 1994-04-28 | 2002-02-12 | Fujitsu Limited | Semiconductor device and method of forming the same |
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