JPS599934A - Manufacture of probe card - Google Patents
Manufacture of probe cardInfo
- Publication number
- JPS599934A JPS599934A JP11893882A JP11893882A JPS599934A JP S599934 A JPS599934 A JP S599934A JP 11893882 A JP11893882 A JP 11893882A JP 11893882 A JP11893882 A JP 11893882A JP S599934 A JPS599934 A JP S599934A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- plate
- circuit pattern
- wafer
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Abstract
Description
【発明の詳細な説明】
本発明は半導体ウェファ−のテストに用いるプローブカ
ードの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a probe card used for testing semiconductor wafers.
中心部に顕微鏡による観察のための穴を有する絶縁基板
にその穴を取り囲んで放射状に探針を配設した従来形式
のプローブカードは、その製造に当たって、上記の穴か
ら、その下に置かれたテストすべき半導体ウェファ−の
端子、または端子の配列位置を画いた図形を観察しなが
ら、探針の先端がウェファ−の端子の配列位置に一致す
るよう、各探針の位置調整を行う必要がある。この作業
は、特に最近、ウェファ−の端子数が増大するにおよん
で、ますます長時間を要する複雑な作業となりつつある
だけでなく、このような方法で製造されたプローブカー
ドは、取扱い上の僅かな不注意により探針の位置が変わ
り、探針位置の再調整を要するなどの欠点や、また、ウ
ェファ−の端子がハンプ型の場合には、探針が滑りをお
こずなどの欠点がある。Conventional probe cards have probes arranged radially around an insulating substrate with a hole in the center for observation using a microscope, surrounding the hole. During manufacture, a probe card is manufactured by inserting a probe into the hole through the hole and placing the probe under the hole. It is necessary to adjust the position of each probe so that the tip of the probe matches the arrangement position of the wafer's terminals while observing the terminals of the semiconductor wafer to be tested or the diagram depicting the arrangement position of the terminals. be. Not only is this process becoming increasingly time-consuming and complex, especially as the number of terminals on wafers increases, but probe cards manufactured in this way are also difficult to handle. There are disadvantages such as the position of the probe changing due to slight carelessness, requiring readjustment of the probe position, and also disadvantages such as the tip slipping if the wafer terminal is a hump type. be.
本発明は、以上のような欠点を取り除き、つ工ファーの
端子数や、端子配列パターンの複雑性に関係なく一定の
作業工程で、ウェファ一端子への接触片間の相対的位置
関係がずれることのない、しかも、端子がハンプ型であ
っても接触子に滑りを生しない、プローブカードの製造
方法を提供することを目的としている。The present invention eliminates the above-mentioned drawbacks and eliminates the problem in that the relative positional relationship between the contact pieces on one wafer terminal deviates during a certain work process regardless of the number of terminals on the wafer or the complexity of the terminal arrangement pattern. It is an object of the present invention to provide a method for manufacturing a probe card that does not cause slippage on contacts even if the terminals are hump-shaped.
以」二の目的のために本発明は、弾性を有する絶縁体上
に、ウェファ−の端子とそれにつながるリード部分のパ
ターンを金属のフォトエツチング法により形成する工程
と、面上に上記パターンが形成された絶縁体をプリント
配線基板上に固着し、上記のパターンとプリント配線と
の間に所定の電気接続を行う工程から成り立っている。For the following two purposes, the present invention includes a step of forming a pattern of a wafer terminal and a lead portion connected thereto on an elastic insulator by a metal photoetching method, and a step of forming the pattern on the surface. The method consists of the steps of fixing the printed insulator onto a printed wiring board and making a predetermined electrical connection between the pattern and the printed wiring.
以下に本発明の実施例を図面に基づいて説明する。Embodiments of the present invention will be described below based on the drawings.
まず、第1図に示すように、厚さQ、2mmの銅板1に
フメトレジストとして例えばコダノク社製マイクロレジ
スト752を塗り、それにテストすべき半導体ウェファ
−の端子パターン3と、それらを外部回路に接続するた
めのリード部のパターン4とから成る回路パターンを、
その部分が感光するように写真焼付けした後、例えばコ
ダノク社のマイクロレジスト・ディヘロノバーで現像し
て回路パターン以外の部分の不用レジストを除去する。First, as shown in FIG. 1, a copper plate 1 with a thickness Q of 2 mm is coated with a fumetresist such as Microresist 752 manufactured by Kodanok Co., Ltd., and the terminal pattern 3 of the semiconductor wafer to be tested is connected to the external circuit. A circuit pattern consisting of pattern 4 of the lead part for
After photo-printing so that the area is exposed to light, it is developed using, for example, Kodanok's Microresist Diheronova to remove unnecessary resist from areas other than the circuit pattern.
第2図はこの段階における銅板上のフメトレジストの付
着状態を、第1図のラインLに沿った断面について示し
ている。次に銅板1の裏側より、端子パターン部に相当
する部分に、第3図に示すように弾性板5として厚さ2
寓諷のゴムと、厚さ11のプラスチックの補強板6を貼
付した後、銅板1にエツチングをほどこしく第4図)、
さらに、銅表面に残留するフォトレジストをコダノク社
のマイクロレジスト除去液を用いて除去すると、第5図
に示すように、弾性板5の表面に銅の端子パターンが形
成される。これを斜め上方より望む斜視図を第6図に示
す。第6図において、回路パターンは銅板1のエツチン
グにより形成されているわけであるが、ここでは記号1
を用いず、回路パターン各部に第1図の端子パターンお
よびリード部のパターンに相当して記号3 (端子)お
よび記号4 (リード)を用いてむ゛る。これを第7図
に示すように、あらかしめ用意されたプリント配線基板
7の上に接着固定し、各リード部4と、プリン1−配線
基板7の所定の配線8との間に電気的接続を行って、本
発明の製造方法によるプローブカードが得られる。第8
図は、第7図のラインMに沿った、プローブカード7の
断面を示す。FIG. 2 shows the state of adhesion of the fumetresist on the copper plate at this stage in a cross section taken along line L in FIG. Next, as shown in FIG.
After pasting the rubber and plastic reinforcing plate 6 with a thickness of 11, etching is applied to the copper plate 1 (Fig. 4).
Furthermore, when the photoresist remaining on the copper surface is removed using a microresist removal solution manufactured by Kodanok, a copper terminal pattern is formed on the surface of the elastic plate 5, as shown in FIG. A perspective view of this from diagonally above is shown in FIG. In FIG. 6, the circuit pattern is formed by etching the copper plate 1, and here it is indicated by the symbol 1.
Instead, symbols 3 (terminal) and 4 (lead) are used for each part of the circuit pattern, corresponding to the terminal pattern and lead pattern in FIG. 1. As shown in FIG. 7, this is adhesively fixed onto a pre-prepared printed wiring board 7, and an electrical connection is made between each lead part 4 and a predetermined wiring 8 of the printed wiring board 7. By doing this, a probe card according to the manufacturing method of the present invention is obtained. 8th
The figure shows a cross section of the probe card 7 along line M in FIG.
以」二のように、本発明によれば、テストすべきウェフ
ァ−の端子への接触子が、端子の数や配列パターンの複
雑性に関係なく、一定のフォトエツチングの工程で得ら
れ、接触子相互間にずれを生ずることもない。また、本
発明に基づく方法で製造されたプローブカードを用いれ
ば、ウェファ−のテストに当たっての、接触子とウェフ
ァ一端子との間の位置整合に際しても、ウェファ−とプ
ローブカードの2次元的位置関係を一度決定しておけば
よく、従来のプローブカードの場合のように、顕微鏡に
より探側とウェファ一端子間の接触を、各探針毎に監視
、調整する必要がない。As described above, according to the present invention, the contacts to the terminals of the wafer to be tested can be obtained by a constant photoetching process, regardless of the number of terminals or the complexity of the arrangement pattern. There is no difference between the children. Furthermore, if the probe card manufactured by the method based on the present invention is used, the two-dimensional positional relationship between the wafer and the probe card can be adjusted even when positioning the contact between the contact and one terminal of the wafer during wafer testing. need only be determined once, and there is no need to use a microscope to monitor and adjust the contact between the probe side and the wafer terminal for each probe, as is the case with conventional probe cards.
第1図は本発明実施例においてフォトエツチングすべき
パターンを示す。第2図、第3図はフォトエツチング実
施の準備過程を説明するための図である。第4図はフォ
トエツチングにより弾性板上に形成されたパターンの断
面図である。第5図および第6図は残留フォトレジスト
が除去され、弾性板上に形成された銅のパターンの、そ
れぞれ断面図および斜視図である。第7図および第8図
はそれぞれ本実施例により製造されたプローブカードの
平面図および断面図である。
■・・・銅板、 2・・・フォトレジスト、3
・・・端子パターン、4・・・リードパターン、5・・
・弾性板、 6・・・補強板、7・・・プリント
配線基板、
8・・・プリント配線。
特許出願人 日本電子材料株式会社
代 理 人 弁理士 西1) 新
手続補正書 動式)
昭和57年 特許層 第118938号2、発明の名
称
プローブカードの製造方法
3、補正をする者
事件との関係 特許出願人
住所 兵庫県尼崎市口田中宇野上167の10氏名
日本電子材料株式会社
代表者 大久保昌男
4、代理人FIG. 1 shows the pattern to be photoetched in an embodiment of the invention. FIGS. 2 and 3 are diagrams for explaining the preparation process for photoetching. FIG. 4 is a cross-sectional view of a pattern formed on an elastic plate by photoetching. Figures 5 and 6 are cross-sectional and perspective views, respectively, of the copper pattern formed on the elastic plate after the residual photoresist has been removed. FIGS. 7 and 8 are a plan view and a sectional view, respectively, of a probe card manufactured according to this example. ■...Copper plate, 2...Photoresist, 3
...Terminal pattern, 4...Lead pattern, 5...
- Elastic board, 6... Reinforcement board, 7... Printed wiring board, 8... Printed wiring. Patent Applicant Japan Electronic Materials Co., Ltd. Agent Patent Attorney Nishi 1) New Procedural Amendment (Movement) 1981 Patent Layer No. 118938 2, Title of Invention Method of Probe Card Manufacturing 3, Amendment to Person Case Related Patent Applicant Address 167 Unogami, Kuchitanaka, Amagasaki City, Hyogo Prefecture 10 names
Japan Electronic Materials Co., Ltd. Representative Masao Okubo 4, Agent
Claims (1)
半導体ウェファ−の端子パターンとそれら端子パターン
につながってリード部を成すパターンとから成る回路パ
ターンを上記フォトレジストに写真焼付した後、上記回
路パターン以外の部分のフォトレジストを除去し、上記
金属板の、フォトレジストを塗布しなかった側の面に弾
性を有する絶縁板を貼付してから、上記金属板に上記回
路パターンを有する側よりエツチングをほどこして上記
回路パターンを示す金属部分を上記絶縁板」二に残留形
成させた後、金属部分表面上に残るフォトレジストを除
去し、上記絶縁板をプリント配線基板」二に固着し、上
記回路パターンのリード部を上記プリント配線基板の所
定の配線に電気接続することによってプローブカードを
形成させる、プローブカードの製造方法。A photoresist is applied to one side of a metal plate, and a circuit pattern consisting of a terminal pattern of a semiconductor wafer to be tested and a pattern connected to the terminal pattern to form a lead part is photoprinted on the photoresist, and then the circuit pattern is printed on the photoresist. After removing the photoresist from other parts, attaching an elastic insulating plate to the side of the metal plate on which the photoresist was not applied, and etching the metal plate from the side with the circuit pattern. After the metal portion showing the circuit pattern is left on the insulating plate 2, the photoresist remaining on the surface of the metal portion is removed, the insulating plate is fixed to the printed wiring board 2, and the circuit pattern is formed on the insulating plate 2. A method for manufacturing a probe card, comprising electrically connecting a lead portion of the probe card to a predetermined wiring of the printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11893882A JPS599934A (en) | 1982-07-07 | 1982-07-07 | Manufacture of probe card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11893882A JPS599934A (en) | 1982-07-07 | 1982-07-07 | Manufacture of probe card |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS599934A true JPS599934A (en) | 1984-01-19 |
JPS6222529B2 JPS6222529B2 (en) | 1987-05-19 |
Family
ID=14748941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11893882A Granted JPS599934A (en) | 1982-07-07 | 1982-07-07 | Manufacture of probe card |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS599934A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62233774A (en) * | 1986-04-03 | 1987-10-14 | Matsushita Electric Ind Co Ltd | Inspecting method for circuit board |
JPH0462479A (en) * | 1990-06-29 | 1992-02-27 | Sharp Corp | Electric inspecting method for semiconductor device |
US5412329A (en) * | 1991-11-18 | 1995-05-02 | Tokyo Electron Yamanashi Limited | Probe card |
WO1995034000A1 (en) * | 1994-06-03 | 1995-12-14 | Hitachi, Ltd. | Connecting device and its manufacture |
US20110159444A1 (en) * | 2006-04-14 | 2011-06-30 | Kabushiki Kaisha Nihon Micronics | Method for manufacturing probe sheet |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132181A (en) * | 1974-09-11 | 1976-03-18 | Matsushita Electric Ind Co Ltd | Handotaisoshisokuteiyopuroobubarinoseizohoho |
JPS51121267A (en) * | 1975-04-17 | 1976-10-23 | Seiko Epson Corp | Semiconductor wafer measuring device |
-
1982
- 1982-07-07 JP JP11893882A patent/JPS599934A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132181A (en) * | 1974-09-11 | 1976-03-18 | Matsushita Electric Ind Co Ltd | Handotaisoshisokuteiyopuroobubarinoseizohoho |
JPS51121267A (en) * | 1975-04-17 | 1976-10-23 | Seiko Epson Corp | Semiconductor wafer measuring device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62233774A (en) * | 1986-04-03 | 1987-10-14 | Matsushita Electric Ind Co Ltd | Inspecting method for circuit board |
JPH0462479A (en) * | 1990-06-29 | 1992-02-27 | Sharp Corp | Electric inspecting method for semiconductor device |
US5412329A (en) * | 1991-11-18 | 1995-05-02 | Tokyo Electron Yamanashi Limited | Probe card |
WO1995034000A1 (en) * | 1994-06-03 | 1995-12-14 | Hitachi, Ltd. | Connecting device and its manufacture |
US20110159444A1 (en) * | 2006-04-14 | 2011-06-30 | Kabushiki Kaisha Nihon Micronics | Method for manufacturing probe sheet |
US8202684B2 (en) * | 2006-04-14 | 2012-06-19 | Kabushiki Kaisha Nihon Micronics | Method for manufacturing probe sheet |
Also Published As
Publication number | Publication date |
---|---|
JPS6222529B2 (en) | 1987-05-19 |
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