JPS5998649U - Chippukiyariya - Google Patents

Chippukiyariya

Info

Publication number
JPS5998649U
JPS5998649U JP20005082U JP20005082U JPS5998649U JP S5998649 U JPS5998649 U JP S5998649U JP 20005082 U JP20005082 U JP 20005082U JP 20005082 U JP20005082 U JP 20005082U JP S5998649 U JPS5998649 U JP S5998649U
Authority
JP
Japan
Prior art keywords
holes
electrode pads
pads
chippukiyariya
connection pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20005082U
Other languages
Japanese (ja)
Inventor
透 高田
正雄 鈴木
森上　義博
Original Assignee
京セラ株式会社
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラ株式会社, 日本電信電話株式会社 filed Critical 京セラ株式会社
Priority to JP20005082U priority Critical patent/JPS5998649U/en
Publication of JPS5998649U publication Critical patent/JPS5998649U/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａ、　　ｂはそれぞれ本案によるチップキャリア
の上面と下面を示したもの、第２図は第１図ａにおける
Ｘ−Ｘ線断面を示したものである。 １：チップキャリア、２：マウント領域、３：電極パッ
ド、４．６：スルーホール、Ｒ：抵抗、Ｗ：ワイヤ。−FIGS. 1a and 1b show the top and bottom surfaces of the chip carrier according to the present invention, respectively, and FIG. 2 shows a cross section taken along the line X--X in FIG. 1a. 1: Chip carrier, 2: Mount area, 3: Electrode pad, 4.6: Through hole, R: Resistor, W: Wire. −

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミック材などの絶縁体板の上面、下面の各々に複数
個の電極パッド、接続パッドを形成し、２　　　　これ
ら各電極パッド、接続パッドを相互にスルーホールで導
通させるとともに、上記絶縁体板のほぼ中央に形成した
半導体チップを載置するマウント領域に複数個のスルー
ホールを設けたことを特徴とするチップキャリア。A plurality of electrode pads and connection pads are formed on each of the upper and lower surfaces of an insulator plate made of ceramic material, etc., and the electrode pads and connection pads are electrically connected to each other through through holes. A chip carrier characterized in that a plurality of through holes are provided in a mounting area formed in the center on which a semiconductor chip is placed.
JP20005082U 1982-12-22 1982-12-22 Chippukiyariya Pending JPS5998649U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20005082U JPS5998649U (en) 1982-12-22 1982-12-22 Chippukiyariya

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20005082U JPS5998649U (en) 1982-12-22 1982-12-22 Chippukiyariya

Publications (1)

Publication Number Publication Date
JPS5998649U true JPS5998649U (en) 1984-07-04

Family

ID=30425582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20005082U Pending JPS5998649U (en) 1982-12-22 1982-12-22 Chippukiyariya

Country Status (1)

Country Link
JP (1) JPS5998649U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155973A (en) * 1974-06-07 1975-12-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155973A (en) * 1974-06-07 1975-12-16

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