JPS5996953U - switching circuit - Google Patents
switching circuitInfo
- Publication number
- JPS5996953U JPS5996953U JP19263682U JP19263682U JPS5996953U JP S5996953 U JPS5996953 U JP S5996953U JP 19263682 U JP19263682 U JP 19263682U JP 19263682 U JP19263682 U JP 19263682U JP S5996953 U JPS5996953 U JP S5996953U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output signal
- input
- logic circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は信号の切替アルゴリズムの一例を示す状態遷移
図、第２図は本考案の一実施例を示すブヮツク図、第３
図は第２図の動作を説明するための波形図である。Fig. 1 is a state transition diagram showing an example of a signal switching algorithm, Fig. 2 is a book diagram showing an embodiment of the present invention, and Fig. 3 is a state transition diagram showing an example of a signal switching algorithm.
The figure is a waveform diagram for explaining the operation of FIG. 2.
Claims (1)
択信号に対応して接続する選択回路と、出力信号の障害
を検出する障害検出回路と、前記障害検出回路の出力信
号の発生点を抽出する微分回路と、前記障害検出回路の
出力信号を一方の入力とする第１の論理回路と、前記第
１の論理回路の出力信号を一方の入力とし、前記微分回
路の出力信号を他方の入力とする第２の論理回路と、前
記第２の論理回路の出力信号を計数し、前記選択回路に
選択信号を与える計数回路と、前記第２の論理回路の出
力信号を遅延し、前記第１の論理回路の他舅の入力信号
とする遅延回路とを有する計とを特徴とする切替回路。a selection circuit that connects one of the plurality of input terminals and one output terminal in accordance with a selection signal; a fault detection circuit that detects a fault in the output signal; and a generation point of the output signal of the fault detection circuit. a first logic circuit that takes the output signal of the fault detection circuit as one input, and a differentiation circuit that takes the output signal of the first logic circuit as one input and the output signal of the differentiation circuit as the other input. a second logic circuit that counts the output signal of the second logic circuit and provides a selection signal to the selection circuit; and a counter circuit that delays the output signal of the second logic circuit; and a delay circuit for inputting an input signal to the other half of the first logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19263682U JPS5996953U (en) | 1982-12-20 | 1982-12-20 | switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19263682U JPS5996953U (en) | 1982-12-20 | 1982-12-20 | switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5996953U true JPS5996953U (en) | 1984-06-30 |
| JPS6324681Y2 JPS6324681Y2 (en) | 1988-07-06 |
Family
ID=30414519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19263682U Granted JPS5996953U (en) | 1982-12-20 | 1982-12-20 | switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5996953U (en) |
-
1982
- 1982-12-20 JP JP19263682U patent/JPS5996953U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324681Y2 (en) | 1988-07-06 |
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