JPS5986234A - Quality evaluation of diffused wafer - Google Patents

Quality evaluation of diffused wafer

Info

Publication number
JPS5986234A
JPS5986234A JP19521282A JP19521282A JPS5986234A JP S5986234 A JPS5986234 A JP S5986234A JP 19521282 A JP19521282 A JP 19521282A JP 19521282 A JP19521282 A JP 19521282A JP S5986234 A JPS5986234 A JP S5986234A
Authority
JP
Japan
Prior art keywords
junction
type
wafer
leakage current
reverse leakage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19521282A
Other languages
Japanese (ja)
Inventor
Hidekatsu Ito
伊藤 秀克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19521282A priority Critical patent/JPS5986234A/en
Publication of JPS5986234A publication Critical patent/JPS5986234A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To obtain an improving method for discriminating the propriety of the bonding property when a P-N junction is formed by diffusing an impurity in the following steps by measuring the reverse leakage current of the P-N junction formed between layers by a heat treatment of specific conditions. CONSTITUTION:A P-N junction is formed by heat treating a silicon wafer formed by laminating two layers of P type having different densities at temperatures of 430-500 deg.C for the period required to invert only the low density side to N type, a reverse leakage current is measured for the junction, thereby evaluating the quality of the wafer and particularly evaluating the junction characteristics. For example, a diffused wafer 11 which becomes an N type layer 11a from the low density side P type layer is formed by heat treating it at 470 deg. for 13hr in nitrogen atmosphere. After a masking is executed by oxidation resistance wax, a mesa groove 12 is formed by mesa etching in depth isolated in N type layers from each other for approx. 2min with etchant having fluoric acid:acetic acid:nitric acid=1:1:2, and the wax is removed by Trichlene. Then, wirings of diode curve tracer 5 are connected to measure the reverse leakage current of the P-N junction.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は拡散ウエノ・の品質評価方法番こ力)力)す
、特にpNP )ランジスタ、ダイオード等の製造−ご
用いられ、るP型シリコン基板に基板よりも高濃度のP
型不純物を拡散した拡散ウエノ1の品質評価方法に関す
る。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a method for evaluating the quality of diffusion wafers, especially for the production of pNP transistors, diodes, etc. has a higher concentration of P than the substrate.
The present invention relates to a method for evaluating the quality of a diffused wafer 1 in which mold impurities are diffused.

〔゛発明の技術的背景〕[゛Technical background of the invention]

従来、主としてPNP )ランジスタの製造に第1図に
示す導電型がP型のシリコンウェハ(1a)にこれより
も高濃度にP型拡散を施してP型拡散層(1b)を有す
る拡散ウェハ(1)が用いられる。この拡散ウェハはP
型シリコンウェハ(以降シリコンウェハをウェハと略称
)をB!0.のイソプロピルアルコール溶液中に浸漬し
たのち、いわゆるデポジション、スランピング方式によ
り高温長時間拡散を施し、ついで一方の主面側の拡散層
を#1000ラッピングとミラーラッピングにより除去
して形成される。通常この場合の拡散は拡散炉にて12
50′〜1300℃の高温で、かつ150〜200時間
の長時間の熱処理により行なわれるため、この拡散炉か
らの汚染等ζこより、後の工程でP型の第1層中にN型
不純物拡散を施してPN接合を形成したとき、逆方向洩
れ電流が異常に大きくなり製品の魅気的特性を満足しな
い場合があるので、後工程に移る前にその品質を評価し
保証する必袂がある。
Conventionally, to manufacture mainly PNP transistors, a silicon wafer (1a) whose conductivity type is P type as shown in FIG. 1) is used. This diffusion wafer is P
Type silicon wafer (hereinafter silicon wafer is abbreviated as wafer) is B! 0. After being immersed in an isopropyl alcohol solution, diffusion is performed at high temperature for a long time using a so-called deposition and slumping method, and then the diffusion layer on one main surface side is removed by #1000 lapping and mirror lapping. Normally, diffusion in this case is carried out in a diffusion furnace at 12
Since the heat treatment is carried out at a high temperature of 50' to 1300°C and for a long time of 150 to 200 hours, contamination from this diffusion furnace occurs. Therefore, in a later process, N-type impurities are diffused into the P-type first layer. When a PN junction is formed by applying this process, the reverse leakage current may become abnormally large and the attractive characteristics of the product may not be satisfied, so it is necessary to evaluate and guarantee its quality before proceeding to the subsequent process. .

従来、その品質を保証する手段として、第1図に示す評
価しようとするウェハの母体ロットより抜取りし、第2
図1al〜ldlに示す工程によって品質の評価を行な
っていた。すなわち、抜敗りしたウェハ(1)にCVD
法によりリン珪酸ガラス(2)を形成しく図1al )
 、ついで、1100−1250℃でリン(P)を拡散
してPN接合(31を形成しく図(b))たのぢ、メサ
エッチングによりメサS+41 、141・・・を形成
しく図1cl ) 、これにダイオードカーブトレーサ
15)の配線を施して測定する(図1d))ものである
Conventionally, as a means of guaranteeing the quality of wafers, samples were taken from the base lot of wafers to be evaluated as shown in Fig.
The quality was evaluated by the steps shown in FIGS. 1al to 1dl. In other words, CVD is applied to the failed wafer (1).
(Figure 1al)
Then, phosphorus (P) was diffused at 1100-1250°C to form a PN junction (Figure (b)), and mesa etching was performed to form mesas S+41, 141, etc. (Figure 1cl). The diode curve tracer 15) is wired to perform the measurement (Fig. 1d)).

〔背景技術の問題点〕− 上記従来の技術によると、拡散ウェハを評価するのにN
型拡散層を形成して行なうため、この拡散層形成に11
00〜1250℃の、高温熱処理を必要とする。この熱
処理にあたり、拡散炉からの新たな汚染や、新たな結晶
欠陥の誘発を生じて正しい評価がなされない欠点がある
。才た、N型拡散層形成のための高温用の拡散炉や、特
別の拡散層を必要とし高価につくなどの欠点がある。
[Problems with background technology] - According to the above-mentioned conventional technology, it takes N to evaluate a diffusion wafer.
Since this is done by forming a type diffusion layer, 11
Requires high-temperature heat treatment of 00 to 1250°C. This heat treatment has the drawback of causing new contamination from the diffusion furnace and induction of new crystal defects, which prevents accurate evaluation. However, there are drawbacks such as the need for a high-temperature diffusion furnace for forming an N-type diffusion layer and a special diffusion layer, which is expensive.

〔発明の目的〕[Purpose of the invention]

この発明は上記従来の欠点に鑑み、P型シリコン基板に
基板よりも高濃度のP型不純物を1主面に拡散した構造
のウェハの品質、就中、以下の工程でN型不純物の拡散
を施してPN接合が形成されたときの接合特性の良否を
判定する改良方法を提供する。
In view of the above-mentioned conventional drawbacks, this invention aims to improve the quality of a wafer having a structure in which a P-type impurity is diffused on one main surface of a P-type silicon substrate at a higher concentration than that of the substrate. Provided is an improved method for determining the quality of the bonding characteristics when a PN junction is formed.

〔発明の概要〕[Summary of the invention]

シリコン中に存在する酸素は450℃伺近の熱処理を施
すとドナーを発生することが知られている。
It is known that oxygen present in silicon generates donors when it is subjected to heat treatment at temperatures close to 450°C.

この性質を利用し、異なる濃度を有するP型の2層が積
層するシリコンウェハについて、430〜500℃の温
度で低濃度側のみがN型に反転するに要する時間だけ熱
処理を施してPN接合を形成し、この接合について逆方
向洩れ電流を測定することにより、このウェハの品質評
価、就中接合特性を評価する方法である。
Taking advantage of this property, a silicon wafer in which two P-type layers with different concentrations are stacked is heat-treated at a temperature of 430 to 500°C for the time required for only the low concentration side to be inverted to N-type to form a PN junction. This is a method for evaluating the quality of this wafer, especially the bonding characteristics, by forming a wafer and measuring the reverse leakage current of this bond.

〔発明の実施例〕[Embodiments of the invention]

次にこの発明を1実施例につき図■]を参照して詳細に
説明する。評価に用いたウェハは、直径76朋、厚さ5
00μm、抵抗率16〜’1QtJ側のP型シリコン基
赦゛をB、0.のイソプロピルアルコール溶液に浸漬し
たのち乾燥し、1285〜でデポジションとスランピン
グを施し両主面から深さ190μm9表面濃度I X 
102°/6−にボロンの拡散層を形成し、その片側の
拡散層を除去したのち厚さ230μmに片面鏡面研摩形
成して第1図に示された拡散ウエノ1を得る。この拡散
ウェハでそのデポジションとスランピングのロフトの異
なる40ツト、すなわち。
Next, one embodiment of the present invention will be explained in detail with reference to FIG. The wafer used for evaluation had a diameter of 76 mm and a thickness of 5 mm.
00μm, resistivity 16~'1QtJ side P-type silicon base is B, 0. After being immersed in an isopropyl alcohol solution of
A boron diffusion layer is formed at 102°/6-, and after removing the diffusion layer on one side, mirror polishing is performed on one side to a thickness of 230 μm to obtain the diffusion layer 1 shown in FIG. This diffusion wafer has 40 different lofts for its deposition and slumping, ie.

Aロット、Bロット、Cロット、Dロットに対し評価を
行なった。
Evaluation was performed on A lot, B lot, C lot, and D lot.

すなわち、各ロフトの母体約90枚ずつのうちより2枚
ずつを抜取りし、第3図1al〜lclに示す工程によ
って品質評価を行なった。まず、窒素雰囲気中で470
℃、13時間熱処理を施す(図(a))。
That is, two sheets were extracted from each loft out of about 90 sheets, and quality evaluation was performed according to the steps shown in FIG. 3 1al to 1cl. First, in a nitrogen atmosphere, 470
℃ for 13 hours (Figure (a)).

これによって低鍵度側P層がN層(lla)になった拡
散ウニハリが形成される。次に耐酸性ワックスにJ: 
リ4 RI角のマスキングを5 aysピッチで施した
のち、ぶつ酸:さく酸(CH,C0OH) :硝酸()
INO,)=:1:1:2になるエツチング液で約2分
間、N層が互いに分離される深さにメサエッチングを施
してメサ溝(臣を形成し、ついでワックスをトリクレン
によって除去する(図(h))。次に、ダイオードカー
ブトレーサ(5)の配線を施してPN接合の逆方向洩れ
電流を測定する(図(C))。この結果でソフトブレー
クダウンしているものは不良品ロット、ハードブレーク
ダウンしているものは良品ロフトと判定する。
As a result, a diffusion unihari is formed in which the P layer on the low key degree side becomes the N layer (lla). Next, add acid-resistant wax to J:
4 After masking the RI angle at a 5 ays pitch, oxycarboxylic acid (CH, C0OH): nitric acid ()
Mesa etching is performed to a depth where the N layers are separated from each other using an etching solution of INO, )=1:1:2 for about 2 minutes to form a mesa groove, and then the wax is removed using trichane. (Figure (h)). Next, wire the diode curve tracer (5) and measure the reverse leakage current of the PN junction (Figure (C)). If the result shows soft breakdown, it is a defective product. Lofts with hard breakdown are judged to be good quality lofts.

叙上の如くしてダイオードカーブトレーサで逆方向の洩
れ電流をウェハ内に10点を選び1lll定した結果を
第5図に示す。この図から明らかなようにAロットは不
良品、B−Dロットはいずれも良品と判定された。
As described above, the leakage current in the reverse direction was determined at ten points on the wafer using a diode curve tracer, and the results are shown in FIG. As is clear from this figure, lot A was determined to be a defective product, and lots BD were both determined to be good products.

〔発明の効果〕〔Effect of the invention〕

この発明によると、拡散ウェハの品質、 特に接合特性
を評価するにあたって、高温熱処理によるN型不純物の
拡散を必要とせず低温熱処理のみでよい。これにより次
にあげる利点かある。
According to this invention, when evaluating the quality of a diffusion wafer, especially the bonding characteristics, it is only necessary to perform low-temperature heat treatment without requiring diffusion of N-type impurities by high-temperature heat treatment. This has the following advantages.

(11PN接合を形成して品質の評価を行なうためのN
型層の形成が、430〜500℃の低温熱処理によるド
ナー発生によっているので、高錨熱処理の汚染や結晶欠
陥の誘発等の影響が無視でき正しい評価が可能である。
(11N for forming PN junction and evaluating quality)
Since the mold layer is formed by donor generation through low-temperature heat treatment at 430 to 500° C., the effects of high-anchor heat treatment such as contamination and induction of crystal defects can be ignored and accurate evaluation is possible.

これを確認するため番こ笑施例で述べたA−Dロットの
拡散ウニ/’%の各々からさらに2枚ずつを抜取りし、
従来の方式で形成したPN接合の逆方向洩れ電流を測定
した結果を示す第4図を見ると、Aロットノ不良(洩し
電流過大)は明確に認められるが、B−D口′ノドも洩
れ電流がやや大きく、良品と不良品との区別がしにくく
なっているが、これはN型層形成の際の加熱処理時に受
けた汚染等の影響によるものと思われる。これに対し、
この発明の方式による洩れ電流を示す第5図ではA口゛
ントは不良、R−Dロットは良品で、両者の間番こは明
確な差が認められ判定しやすく、最終製品書ごつき測定
した■。1.o(ベース・コレクタ間電流)値のロフト
毎の分布を示す第6図ともよく合致している。
To confirm this, two more sheets were taken from each of the diffusion sea urchins/'% of lots A to D mentioned in the Bankosho example.
Looking at Figure 4, which shows the results of measuring the reverse leakage current of a PN junction formed using the conventional method, it is clearly seen that there is a defect in the A-lot (excessive leakage current), but there is also leakage at the B-D opening. The current was somewhat large, making it difficult to distinguish between good and defective products, but this is probably due to the influence of contamination during the heat treatment during the formation of the N-type layer. On the other hand,
In Figure 5, which shows the leakage current according to the method of this invention, the A lot is defective and the R-D lot is good. I did ■. 1. It also matches well with FIG. 6, which shows the distribution of o (base-collector current) values for each loft.

(2)従来の方式では例えばリンのようなN型の不純物
の拡散源および、これに付随する設備力I必要であるが
、本発明では不要である。
(2) In the conventional method, a diffusion source of an N-type impurity such as phosphorus and associated equipment power I are necessary, but this is not necessary in the present invention.

(31従来の方式ではN型層の形成のために拡散炉は1
100〜1250’C程度の高温用のものを必要とした
が、本発明では430〜500℃程度の低温でよいので
経済的であると同時に基板の変型等に対し有効であるな
どの利点もある。
(31 In the conventional method, one diffusion furnace is used to form the N-type layer.
A high-temperature device of about 100 to 1250'C was required, but in the present invention, a low temperature of about 430 to 500'C is required, so it is economical and has the advantage of being effective against deformation of the board, etc. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は被評価ウェハの断面図、第2図talないしl
dlは従来の拡散ウェハの品質評価方法を説明するため
のいずれも断面図、第3図ialないしletは本発明
にがかる1実施例の方法を説明するためのいずれも断面
図、第4図は従来方法によるPN接合の逆方向洩れ電流
の測定結果を示す線図、第5図は1実施例の方法による
PN接合の逆方向洩れ電流の測定結果を示す線図、第6
図は製品につき逆方向洩れ電流(Icno )を測定し
た結果を示す線図である。 la      P型シリコン基板 5      ダイオードカーブトレーサリ     
 拡散ウエノ) 11a      拡散ウェハのNN l2      メサ溝 代理人 弁理士 井 上 −男 第  1  図 第  2  図 第  3  図 第4図 ロー/r→ hbc。 第5図 第  6  図
Figure 1 is a cross-sectional view of the wafer to be evaluated, and Figure 2 is a sectional view of the wafer to be evaluated.
dl is a cross-sectional view for explaining a conventional diffusion wafer quality evaluation method, FIG. 3 is a cross-sectional view for explaining a method of an embodiment of the present invention, and FIG. FIG. 5 is a diagram showing the measurement results of the reverse leakage current of a PN junction according to the conventional method; FIG.
The figure is a diagram showing the results of measuring the reverse leakage current (Icno) for the product. la P-type silicon substrate 5 Diode curve tracery
Diffusion wafer) 11a NN of diffusion wafer 12 Mesa groove agent Patent attorney Inoue - Male 1st figure 2nd figure 3rd figure 4th row/r → hbc. Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] P型の不純物濃度が3 X 10”〜4×10+6/−
の第1層と、P型で第1NjIよりも高1.N不純物濃
度の1x 1 ()IT〜5 x 1o”/−に拡散形
成された第2層よりなるシリコンウェハ\を、430°
〜500℃で4〜50時間熱処理を施して前記第1層を
N型番こ反転させて第2層との間にPN接合を形成し、
このPN接合の逆方向洩れ電流を1Ill定すること番
こよってこのシリコンウェハの品質評価を行なうことを
特徴とする拡散ウエノ・の品質評価方法。
P-type impurity concentration is 3 x 10” to 4 x 10+6/-
The first layer is P-type and higher than the first NjI. A silicon wafer consisting of a second layer diffused to an N impurity concentration of 1 x 1 ()IT ~ 5 x 1o''/- was heated at 430°.
Heat treatment is performed at ~500° C. for 4 to 50 hours to reverse the N-type number of the first layer and form a PN junction with the second layer;
A method for evaluating the quality of a diffused wafer, characterized in that the quality of the silicon wafer is evaluated by determining the reverse leakage current of the PN junction.
JP19521282A 1982-11-09 1982-11-09 Quality evaluation of diffused wafer Pending JPS5986234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19521282A JPS5986234A (en) 1982-11-09 1982-11-09 Quality evaluation of diffused wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19521282A JPS5986234A (en) 1982-11-09 1982-11-09 Quality evaluation of diffused wafer

Publications (1)

Publication Number Publication Date
JPS5986234A true JPS5986234A (en) 1984-05-18

Family

ID=16337319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19521282A Pending JPS5986234A (en) 1982-11-09 1982-11-09 Quality evaluation of diffused wafer

Country Status (1)

Country Link
JP (1) JPS5986234A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759871A (en) * 1996-07-26 1998-06-02 Advanced Micro Devices, Inc. Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759871A (en) * 1996-07-26 1998-06-02 Advanced Micro Devices, Inc. Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques
US5913106A (en) * 1996-07-26 1999-06-15 Advanced Micro Devices, Inc. Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques
US6037607A (en) * 1996-07-26 2000-03-14 Advanced Micro Devices, Inc. Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques

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