JPS5947738A - Measurement of diffusion layer - Google Patents

Measurement of diffusion layer

Info

Publication number
JPS5947738A
JPS5947738A JP15743582A JP15743582A JPS5947738A JP S5947738 A JPS5947738 A JP S5947738A JP 15743582 A JP15743582 A JP 15743582A JP 15743582 A JP15743582 A JP 15743582A JP S5947738 A JPS5947738 A JP S5947738A
Authority
JP
Japan
Prior art keywords
diffusion layer
type
layer
sample
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15743582A
Other languages
Japanese (ja)
Inventor
Hidekatsu Ito
伊藤 秀克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15743582A priority Critical patent/JPS5947738A/en
Publication of JPS5947738A publication Critical patent/JPS5947738A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Abstract

PURPOSE:To accurately and easily measure diffusion layer of wafer in the manufacturing line and suppress increase of cost for quality control by measuring P-N junction generated through conversion of the area other than the P type diffusion layer to the N type by processing a substrate forming the P type diffusion layer at a lower temperature. CONSTITUTION:An alcohol saturated solution of B2O2 is applied to a single side of P type silicon substrate having resistivity of 15-20OMEGAcm and thickness of 210mum obtained by doping boron with the CZ method. The silicon substrate is heated for 140hr at 1,290 deg.C and a diffusion layer is formed on the P type silicon substrate in the depth of 160mum with the surface concentration of boron of 10<20>pcs/cm<3>. An element thus obtained is used as a sample for measurement. This sample is heated for 12hr at 460 deg.C under a gas of H2, O2, N2 or a mixed gas of them. Thereby the area other the diffused layer of sample is converted into an N type conductive region layer. This sample is then cut into segments having adequate sizes and are polished until a angle of 5 deg.43' can be obtained. After applying the hydrofluoric acid solution to the polishing surface of segment 1, the polishing surface is heated by an infrared lamp for about one minute in order to form a staining film. Depth (h) of diffused layer is obtained from thickness of film using known equation by observing such staining film with a microscope.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は4、シリコンウェハの拡散層の測定力fl[
関し、特に実際の生産ラインにおいてシリコンウェハの
拡散層を簡易にかつ精度よく測定することができる新規
な拡散層測定力6+3H:門するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides 4. a measurement force fl [of a diffusion layer of a silicon wafer].
In particular, the new diffusion layer measuring force 6+3H is used to easily and accurately measure the diffusion layer of a silicon wafer on an actual production line.

〔発明の技術的背景〕[Technical background of the invention]

シリコンウニ・・の不純物拡散層ン・熱拡散やイオン注
入により形+j!7 L、た場合、その拡散層の拡散深
さや非拡散領域層の幅など舎正確f・ζ1lJl定−す
ることは半導体製造の品質管理において極めて重要なこ
とであるC特にアクセプタ不純物を含有して抵抗率0.
5〜5000ΩC7)Jの低濃度P型7リコンウエノ・
に、それよりも高濃度σ)アクセプタ不純物を含有さ庸
た高濃度P型拡散層を形成さ−11−た場合のシリコン
基板について、拡散層の深さン・測定することが難しい
、 従来、このよう外ンリコンウエノ・σ)′I+/、ti
t層の深さを測定するための品質管理的力〃−1左1−
5τ、以下の如き二方法が実施貞力、ているが、これら
の方法は以下に記載するような欠点があるため、よりj
1確でかつ簡易に実施できるとともj(7蒋済的な測定
方法の開発が望まわ、ていた、 〔背景技術の問題点〕 従来、低濃度P型シリコン基板に高濃度P型拡散層を形
成1−たシリコンウェハの拡散層の深さの測定方法と1
.て次の二つの方法が実施されてきた。
Formed by impurity diffusion layer of silicon sea urchin, thermal diffusion and ion implantation! 7 L, it is extremely important to accurately determine the diffusion depth of the diffusion layer and the width of the non-diffused region layer in the quality control of semiconductor manufacturing. Resistivity 0.
5~5000ΩC7) J low concentration P type 7 recon ueno・
Conventionally, it is difficult to measure the depth of the diffusion layer for a silicon substrate in which a highly concentrated P-type diffusion layer containing acceptor impurities is formed. In this way, σ)′I+/, ti
Quality control force for measuring the depth of the t-layer〃-1Left 1-
5τ, the following two methods are viable, but these methods have drawbacks as described below, so they are more difficult to implement.
[Background technology problems] Conventionally, a high concentration P-type diffusion layer was formed on a low concentration P-type silicon substrate. 1- Method for measuring the depth of the diffusion layer of a silicon wafer formed with
.. The following two methods have been implemented.

第一の方法は間接的方法であり、この第一の方法におい
てに、年産ラインで製造され7ているP型シリコンウニ
・・とは別VcN型ウニ・・を測定試料と]−て準備1
−1該N型ウエノ・に該P型つニ・・と同条件の下でP
型不純物を拡散させてPN接合を形成した後、N型ウェ
ハの拡散層の深さを公知のステイニング法や金めつき法
によって測定し、その測定値力・らP型シリコンウェハ
の拡散層の測定値に換算する。
The first method is an indirect method, and in this first method, a VcN type sea urchin, which is different from the P type silicon sea urchin manufactured on the annual production line, is used as a measurement sample.
-1 Under the same conditions as the N-type Ueno and the P-type Tsuni...
After diffusing type impurities to form a PN junction, the depth of the diffusion layer of the N-type wafer is measured by a well-known staining method or gold plating method, and the measured value is the depth of the diffusion layer of the P-type silicon wafer. Convert to measured value.

このような間接的な測定方法によって正確な測定値を得
るためには測定資料たるN型つエノ・の基板濃度がP型
ウェハの基板濃度と合致していなければならないが、実
際の生産ラインにおいてこスtを実現することは困難で
あり、また、このような両ウニ・・の基板濃度の不一致
のほかに、以下の如き拡散層形成時の濃度差増大現象が
加わるため、N型ウェハにおける見掛は測定値とP型つ
ニ・・の真値の間の誤差は一層大きく斤り、ヒr−って
この第一の方法によっては、正確な測定値f qlるこ
とばできない。前記の如き拡散層形/j′y、II″「
1−おける両つjハの濃度差増大現象は、酸化性雰囲気
中でσ)N型不純物の挙動とP型不純物の挙動との差異
1・て;E <ものである。すなわち、酸化r1:雰囲
気中で姐N型不純物の濃度が増人才るのに反(7てp 
7!iリイく鈍物kj、減少する傾向があり、従って、
拡散層形成後には両ウェハの濃度差は一層増大1.て測
定値と真値との誤差を更に一層増大させることになる、
第二の方法は、基板の不純物ffd fuと拡散層の不
純物濃度との濃度勾配に基く広がり抵抗を測定するスフ
”レディングレジスクン′スフ′r1−)法であり、こ
の方法に基いて構成式九だ測定機械が市販さil。
In order to obtain accurate measurement values using this indirect measurement method, the substrate concentration of the N-type wafer, which is the measurement data, must match the substrate concentration of the P-type wafer, but in the actual production line, It is difficult to achieve this, and in addition to this discrepancy in substrate concentration between the two substrates, there is also the phenomenon of increased concentration difference during the formation of the diffusion layer, as described below. The error between the apparent measured value and the true value of P-type Tuni... is even larger, and it is impossible to accurately determine the measured value fql by this first method. Diffusion layer type /j'y, II'' as described above
The phenomenon of increasing concentration difference between both j and c in 1- is the difference between the behavior of σ) N-type impurities and the behavior of P-type impurities in an oxidizing atmosphere. That is, oxidation r1: Although the concentration of N-type impurities increases in the atmosphere (7
7! The dullness tends to decrease, and therefore,
After forming the diffusion layer, the concentration difference between both wafers increases further.1. This will further increase the error between the measured value and the true value.
The second method is the ``Redding Resistance'' method, which measures the spreading resistance based on the concentration gradient between the impurity ffd fu in the substrate and the impurity concentration in the diffusion layer. Nine measuring machines are commercially available.

ている、この第7の方法では第一の方法と異って、N型
ウェハを準備する必要はなく、測定すべきP型つェハ欠
該測定機にセットL7て?lll定すればよいので、第
一の方法よりも正確な測シ;2が”J能であるが、この
方法においても拡散層と基板との濃度勾配が小さい場合
には4〜8μ程度の誤差を生ずる欠点がある上、測定機
械が高価であるため品質管理に要するコストが著しく増
大するという問題点があった。
In this seventh method, unlike the first method, there is no need to prepare an N-type wafer, and there is no need to prepare a P-type wafer to be measured. This method is more accurate than the first method; however, even with this method, if the concentration gradient between the diffusion layer and the substrate is small, the error is about 4 to 8 μ. In addition, there is a problem in that the cost required for quality control increases significantly because the measuring machine is expensive.

〔発明の目的〕[Purpose of the invention]

この発明σ、前記の如き従来方法に存する問題点を解決
し、実際の生産ラインにおいてシリコンウェハの拡散層
をより正確にかつ、簡易に測定することができるととも
に品質管理に要するコストを著しく増大させることのな
い、新規な拡散層測定方法を提供することケ目的とする
This invention σ solves the problems existing in the conventional method as described above, makes it possible to more accurately and easily measure the diffusion layer of a silicon wafer in an actual production line, and significantly increases the cost required for quality control. The purpose of this invention is to provide a novel method for measuring a diffused layer.

〔発明の概要〕[Summary of the invention]

本発明は、単結晶シリコンウェハ・内に存在する酸素の
一部が、該ウェハを低温熱処理した時にドナーとなる現
象に着目して々されたものであり、P型シリコン基板に
P型拡散層を形成した後、°睦基板を低温熱処理するこ
とによりP型拡散層以外の部分’(rN型に転換せしめ
、これにより生じたPN接合を公知のステイニング法や
金めつき法等を用いて測定することにより精度の高い拡
散層測定を可能としたことを特徴とする。熱処理条件に
ついてはシリコン基板の不純物濃度や拡散層の不純物濃
度との関係で種々の値を選択できるが、一般的に550
℃以下で50時間角内の範囲が効果的である。また、シ
リコン基板の不純物m度は抵抗率で05〜5000Ωα
の範囲において選択できろ。
The present invention was developed by focusing on the phenomenon in which some of the oxygen present in a single crystal silicon wafer becomes a donor when the wafer is subjected to low-temperature heat treatment. After forming the substrate, the parts other than the P-type diffusion layer are converted to the rN type by subjecting the substrate to low-temperature heat treatment, and the resulting PN junction is formed using a known staining method, gold plating method, etc. It is characterized by making it possible to measure the diffused layer with high precision by measuring.Various values can be selected for the heat treatment conditions depending on the impurity concentration of the silicon substrate and the impurity concentration of the diffused layer, but in general, 550
C. or less within 50 hours is effective. In addition, the impurity degree of the silicon substrate is 05 to 5000Ωα in terms of resistivity.
You can choose within the range.

〔発明の実施例〕[Embodiments of the invention]

CZ法でボロンドープして得られた抵抗率15〜200
cm %厚さ210 pm (D P型シリコン基板の
片面VcB203のアルコール飽和溶液を塗布した後、
該シリコン基板を1290℃で140時間加p、+y 
1.、、てボロン表面濃度が1020個/n4で160
μmの深さの拡散層をP型シリコン基板に形成し、こ几
に測定試料とした(第1図参照)。
Resistivity 15-200 obtained by boron doping by CZ method
cm% thickness 210 pm (D After coating one side of the P type silicon substrate with an alcohol saturated solution of VcB203,
The silicon substrate was heated at 1290°C for 140 hours with p, +y
1. ,, boron surface concentration is 160 at 1020 pieces/n4
A diffusion layer with a depth of μm was formed on a P-type silicon substrate, and this was used as a measurement sample (see FIG. 1).

第1図の試料を■■2,0゜8N2もしく VJ、こノ
しらの混合ガスの雰囲気中で460℃IF、3>いγ1
2時間熱処理し第2図に示すように該試料の拡散層以外
の部分をN型導電領域層に転換さぜフン、。
The sample in Figure 1 was heated at 460°C IF in a mixed gas atmosphere of 2,0°8N2 or VJ, Konoshira.
Heat treatment was performed for 2 hours to convert the portion of the sample other than the diffusion layer into an N-type conductive region layer as shown in FIG.

前記の如き熱処理後、試料千−適当な小片に力。After heat treatment as described above, the sample was cut into small pieces.

ティングし、その小片1を第6図の如く5°43′の角
度研磨した後、公知のステイニング法によって以下のよ
うに測定を行った。
After polishing the small piece 1 at an angle of 5°43' as shown in FIG. 6, measurements were made as follows using a known staining method.

すなわち、弗化水素500 CC: 、硝酸(、cc・
、純水500 CCからなる弗化水素酸溶液を前記小月
1の角度研磨面に塗布した後、約1分間、該角度研磨面
を赤外線ランプで加熱してステイニング膜街形成させた
。そして、このステイニング膜を顕微鏡で観察して公知
の式によってステイニング膜の厚さから拡散層の深さh
’l求めた。その結果、本発明の測定方法によitば誤
差は1μm以下であった。
That is, hydrogen fluoride 500 CC:, nitric acid (cc.
After applying a hydrofluoric acid solution consisting of 500 cc of pure water to the angle-polished surface of the small moon 1, the angle-polished surface was heated with an infrared lamp for about 1 minute to form a staining film. Then, this staining film is observed under a microscope and the depth h of the diffusion layer is calculated from the thickness of the staining film using a known formula.
'l asked for it. As a result, the error according to the measuring method of the present invention was 1 μm or less.

また、試料となるP型シリコン基板の不純物濃度と熱処
理時間を種々の範囲に変えて同じ方法で拡散層厚さを測
定したところ、やはり同様な結果を得ることができた〇 また、試料とするP型シリコン基板の不純物ドープ方法
′frCZ法でなくFZ法にして試料な形成し、この試
料に対しても前記と同一条件で拡散層の測定を実施して
みたが、同じ結果を得ることができた。
In addition, when we measured the diffusion layer thickness using the same method by varying the impurity concentration and heat treatment time of the P-type silicon substrate used as a sample, we were able to obtain similar results. Impurity doping method for P-type silicon substrate: A sample was formed using the FZ method instead of the frCZ method, and the diffusion layer was measured on this sample under the same conditions as above, but the same results could not be obtained. did it.

〔発明の効果〕〔Effect of the invention〕

以上の結果力・ら、本発明に、t :r+、 [□:1
、公知のスブレディングレジスクン57ブローブi’j
= Jニリもjri 確でかつコストの安価な拡散層測
定力)−ノ、が提供さit、、本発明の方法によノ]、
は、半導体製鎖の製造コストを上昇させることなく品質
を白土することが可能になる。
As a result of the above, in the present invention, t:r+, [□:1
, well-known scrubbing register 57 probe i'j
= Accurate and low-cost measurement of the diffused layer) is provided by the method of the present invention.
This makes it possible to improve the quality of semiconductor chains without increasing the manufacturing cost.

なお、前記実施例でり]ステイニング法を用いる例のみ
ケ示したが、ヌテイニンク゛法1(C代えで公知の金め
つき法や広がり抵抗側511法所−用いで」二い。
In the above embodiments, only examples using the staining method have been shown, but it is also possible to use the staining method 1 (instead of C, a known gold plating method or the spreading resistance side 511 method may be used).

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第6図は本発明の方法の各段階VCも・ける
測定試料の断面図である。 1・・・カッティングした小片。 第1 第2 第3 77鑑′ 179− /1
FIGS. 1 to 6 are cross-sectional views of measurement samples during each step VC of the method of the present invention. 1...A small piece that has been cut. 1st 2nd 3rd 77th edition' 179- /1

Claims (1)

【特許請求の範囲】[Claims] 41 アクセプタ不純物を含有するシリコン基板に、そ
力、よりも高濃度のアクセプタ不純物を拡散若しくはイ
オン注入した場合、該シリコン基板の拡散層若しくはイ
オン注入層の深さ又は非拡散領域層若し7〈は非イオン
注入領域層の幅を測定する方法において、該シリコンウ
ニを430〜520℃で1〜50時間熱処理し、」−配
弁拡散領域層若しくは非イオン注入領域層をN導?b型
に反転させてPN接合を形成し、しかる後に上記深さ又
は上記幅を測定することを特徴とする拡散層測定方法。
41 When a silicon substrate containing an acceptor impurity is diffused or ion-implanted with an acceptor impurity at a higher concentration than that of the silicon substrate, the depth of the diffusion layer or ion implantation layer of the silicon substrate or the non-diffusion region layer or 7 In a method for measuring the width of a non-ion implanted region layer, the silicon sea urchin is heat treated at 430 to 520° C. for 1 to 50 hours, and the valve diffusion region layer or the non-ion implanted region layer is made into an N-conducting layer. A diffusion layer measuring method characterized by forming a PN junction by inverting it to a b-type, and then measuring the depth or the width.
JP15743582A 1982-09-11 1982-09-11 Measurement of diffusion layer Pending JPS5947738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15743582A JPS5947738A (en) 1982-09-11 1982-09-11 Measurement of diffusion layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15743582A JPS5947738A (en) 1982-09-11 1982-09-11 Measurement of diffusion layer

Publications (1)

Publication Number Publication Date
JPS5947738A true JPS5947738A (en) 1984-03-17

Family

ID=15649580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15743582A Pending JPS5947738A (en) 1982-09-11 1982-09-11 Measurement of diffusion layer

Country Status (1)

Country Link
JP (1) JPS5947738A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013189132A1 (en) * 2012-06-21 2013-12-27 中国科学院微电子研究所 Method for determining pn junction depth

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013189132A1 (en) * 2012-06-21 2013-12-27 中国科学院微电子研究所 Method for determining pn junction depth

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