JPS5985858A - Ion implantation device - Google Patents

Ion implantation device

Info

Publication number
JPS5985858A
JPS5985858A JP19663982A JP19663982A JPS5985858A JP S5985858 A JPS5985858 A JP S5985858A JP 19663982 A JP19663982 A JP 19663982A JP 19663982 A JP19663982 A JP 19663982A JP S5985858 A JPS5985858 A JP S5985858A
Authority
JP
Japan
Prior art keywords
ion implantation
silicon wafer
insulating film
gate insulating
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19663982A
Other languages
Japanese (ja)
Inventor
Takanari Tsujimaru
辻丸 隆也
Hidetaro Nishimura
西村 秀太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19663982A priority Critical patent/JPS5985858A/en
Publication of JPS5985858A publication Critical patent/JPS5985858A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/48Ion implantation

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To prevent insulation breakdown in ion implantation to a silicon wafer by irradiating UV light having a wavelength of specific angstrom or below to the SiO2 constituting a gate insulation film. CONSTITUTION:An ion is implanted to a silicon wafer 11 produced by providing a gate insulation film consisting of SiO2 on the surface and providing a gate electrode on the gate insulation film thereby forming a source region and drain region. An opening 21 is provided to a process chamber in the end station part of the device and an UV generator 22 is provided on the outside thereof. UV light having a wavelength of <=1,400 angstrom is applied through the opening 21 to the silicon wafer 11 while the ion is implanted.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造プロセスに係り、4?にMO
8集積回路におけろFET (’ゼ1界効果トランジス
タ)のソース領域、ドレイン領域を形成するイオン注入
装置に関する 〔発明の技術的背景〕 近年、MO8集積回路装置の製造には、ドナーあるいは
アクセプタとなる不純物を半導体ウェーハに打ち込むイ
オン注入が広く用いられている。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a manufacturing process of a semiconductor device, and relates to a manufacturing process of a semiconductor device. MO to
Regarding ion implantation equipment for forming source and drain regions of FET (field effect transistor) in 8 integrated circuits [Technical background of the invention] In recent years, in the manufacture of MO8 integrated circuit devices, donor or acceptor Ion implantation is widely used to implant impurities into semiconductor wafers.

第1図は半導体ウェーハへのイオン注入Y 説明する図
である。シリコンウェーハ1上にフィールド絶縁膜2お
よびゲート絶縁膜3を設け、ゲート絶縁膜3上には導電
性のゲート′五極4が設けであるbここで、フィールド
絶縁膜2、ゲート絶縁膜3は二酸化シリコンで形成する
ことができろ。そしてシリコンウェーハ1上にソース領
域、ドレイン領域5を形成するためにイオンビーム6を
照射f7−+。その際、イオンビーム6はゲート電極4
にも照射されるので、ゲート電極4はイオンかう与えら
れろ電荷?蓄積する。
FIG. 1 is a diagram illustrating ion implantation Y into a semiconductor wafer. A field insulating film 2 and a gate insulating film 3 are provided on a silicon wafer 1, and a conductive gate pentode 4 is provided on the gate insulating film 3. Here, the field insulating film 2 and the gate insulating film 3 are It could be made of silicon dioxide. Then, an ion beam 6 is irradiated f7-+ to form a source region and a drain region 5 on the silicon wafer 1. At that time, the ion beam 6 is applied to the gate electrode 4
Since the gate electrode 4 is also irradiated with ions, the gate electrode 4 is given an ion charge. accumulate.

従来、このイオン注入におけるビーム電流は数μA程度
のものであったが2製I告工程の時間短縮などのためビ
ーム電流はしだいに大ぎくなり、最近では数mA〜数十
mA程度のものになっている。
In the past, the beam current for this ion implantation was about a few μA, but due to factors such as shortening the time of the 2nd I detection process, the beam current has gradually become larger and has recently ranged from several mA to several tens of mA. It has become.

このため、製造工程中にゲート電極に蓄積する電荷は著
しく増大している。また、集積回路装置の高集積化のた
め、ゲート絶縁膜のノVさは薄くなる傾向にある。
For this reason, the amount of charge accumulated in the gate electrode during the manufacturing process increases significantly. Further, as integrated circuit devices become more highly integrated, the voltage resistance of gate insulating films tends to become thinner.

ビーム電流の大電流化とゲート絶縁膜の薄膜化は、ゲー
ト絶縁膜の絶縁破壊の危険性を増大させる。なぜなら、
ビーム電流の大電流化はゲート電極の蓄積電荷の増大ケ
もたらし2ゲート絶縁膜の薄膜化は絶縁耐圧の低下をも
たらすからである。
Increasing the beam current and making the gate insulating film thinner increases the risk of dielectric breakdown of the gate insulating film. because,
This is because an increase in the beam current results in an increase in the charge stored in the gate electrode, and a thinner two-gate insulating film results in a decrease in dielectric breakdown voltage.

例えば、ゲート絶縁)jαの厚さ740OA、破壊電界
’& I X 10’v/cmとすると、ゲート電極に
2X10個/cIIL−の正電荷があると絶縁破壊が発
生する。
For example, assuming that the thickness of the gate insulation (jα) is 740 OA and the breakdown electric field is 10'v/cm, dielectric breakdown will occur if there are 2X10 positive charges/cIIL- in the gate electrode.

このようなゲート絶縁膜の絶縁破壊を防止するために、
従来はシリコンウェーハに陰電子を照射する方法が用い
られており、+X2図および第3図ケ滲照して従来のイ
オン注入装置な説明″fろ。第2図はイオン注入装置の
購成例で、シリコンウェーハ11に打ち込まれるイオン
は、イオン生成装置12で生成され、イオンビーム13
として射出されろ。イオンビーム13はアナライジング
マグネット14%’介してディスク15上に設けたシリ
コンウェーハ11に与えられる。ディスク15には回転
モータ16が設けられ、また、エンドステーション部に
はファラデーケージ17および電子銃18が設げられて
ぃろ0 8g3図は・刊2図に示すイオ〉′注入装置のエンドス
テーション部の拡大図で、牟2図と同−要素は同一符号
で示しである。1シ子統18から射出された電子ビーム
はファラデーケージ171C打ちつけられ、ここで二次
電子19ヲ発生させる。二次電子の−AISはディスク
15上のシリコンウェーハ11に与えられ、ゲート電極
上の正電荷を中和する。′fなゎち4イオンビーム13
によってゲート電極上に蓄積した正電荷は、ファラ・デ
ーケージ17からの二次電子により中和される。このよ
うにしてゲート絶縁膜における絶縁破壊を防止すること
ができろ。
In order to prevent such dielectric breakdown of the gate insulating film,
Conventionally, a method of irradiating a silicon wafer with negative electrons has been used. The ions implanted into the silicon wafer 11 are generated by the ion generator 12 and sent to the ion beam 13.
Be ejected as. The ion beam 13 is applied to the silicon wafer 11 provided on the disk 15 via an analyzing magnet 14%'. A rotary motor 16 is provided on the disk 15, and a Faraday cage 17 and an electron gun 18 are provided on the end station. This is an enlarged view of the part, and the same elements as in Fig. 2 are indicated by the same symbols. The electron beam emitted from the first electron beam 18 hits the Faraday cage 171C, where it generates secondary electrons 19. -AIS of secondary electrons is applied to the silicon wafer 11 on the disk 15 to neutralize the positive charge on the gate electrode. 'f nawachi 4 ion beam 13
The positive charges accumulated on the gate electrode are neutralized by secondary electrons from the Farah day cage 17. In this way, dielectric breakdown in the gate insulating film can be prevented.

〔背景技術の問題点〕[Problems with background technology]

上述の如〈従来装置は、ゲート電り夕の正電荷ケ二次電
子の持つ負電荷で中和てろことによりゲート絶縁膜の絶
縁破壊を防止するものであり、イオン注入の瞳すなわち
ビーム電流の大きさに応じて二次電子の供給脅を変化さ
せなければならない等の問題がある。
As mentioned above, the conventional device prevents dielectric breakdown of the gate insulating film by neutralizing the positive charge of the gate electrode with the negative charge of the secondary electrons, and the pupil of ion implantation, that is, the beam current There are problems such as the need to change the supply threat of secondary electrons depending on the size.

〔発明の目的〕[Purpose of the invention]

本発明は上記の点に鑑みてなされたもので、シリコンウ
ェーハ上のデー)!極に蓄積された正電荷を、負の電子
で中和することによって絶縁破壊を防止するという手段
によらないイオン注入装置を提供することを目的とする
The present invention has been made in view of the above points, and is based on data on silicon wafers. It is an object of the present invention to provide an ion implantation device that does not prevent dielectric breakdown by neutralizing positive charges accumulated in a pole with negative electrons.

〔発明の概要〕[Summary of the invention]

上記の目的を実現するため本発明は、従来装置に紫外線
照射装置を設けろことによってシリコンウェーハにイオ
ン注入している間は紫外線を照射し、ゲート絶縁膜を形
成する二酸化シリコンの導電性を高めろことによってゲ
ート電極上の正電荷な取り除くイオン注入装置を提供す
るものである。
In order to achieve the above object, the present invention provides an ultraviolet irradiation device in a conventional device, thereby irradiating ultraviolet rays during ion implantation into a silicon wafer to increase the conductivity of silicon dioxide forming the gate insulating film. The present invention provides an ion implantation device that removes positive charges on a gate electrode.

〔発明の実施例〕[Embodiments of the invention]

第4図厄よび第5図を参照して本発明の一実施例を説明
する。第4図は一実施例に係るイオン注入装置の構成図
で、第2図と同一の要素は同一符号で示す。イオン注入
装置#のエンドステーション部のプロセスチャンバーに
開口部21?設け、その外側に紫外線発生装置! 22
を設ける。そして、発生した紫外線を開口部21を介し
てシリコンウェーハ1■に与える。なお、プロセスチャ
ンバー内はlX16−5Torr程度以下の真空にされ
ている。
An embodiment of the present invention will be described with reference to FIG. 4 and FIG. 5. FIG. 4 is a block diagram of an ion implantation apparatus according to one embodiment, and the same elements as in FIG. 2 are designated by the same reference numerals. Opening 21 in the process chamber of the end station part of the ion implanter #? Installed and an ultraviolet generator on the outside! 22
will be established. Then, the generated ultraviolet rays are applied to the silicon wafer 1 through the opening 21. Note that the inside of the process chamber is kept in a vacuum of about 1.times.16-5 Torr or less.

第5図はシリコン(Si)と二酸化シリコン(SiOx
)の接合部のエネルギーバンド図で1図から明らかなよ
うに8101のエネルギーギャップは8.9eV程度で
ある。5insに紫外、腺を与えて光導電性をもたせる
ためには、紫外線の波長:々ま。
Figure 5 shows silicon (Si) and silicon dioxide (SiOx).
) As is clear from Figure 1 in the energy band diagram of the junction, the energy gap of 8101 is about 8.9 eV. In order to give 5ins ultraviolet light and photoconductivity, the wavelength of ultraviolet light:

λ= hxC 8°リ  (1) 以下であることが要求される。ここで、ブランク定数:
 h = 6.624XIOJ−see光速 : c 
= 3.OX10’m/s e c電子ポルト : 1
eV = 1.602 XIOJであるから%3i02
のエネルギーギャップヲ8.9eVとすると、(1)式
より紫外線の波長:λは(6) # 1.394 Xl0−’= 1394A(オングス
トローム)となる。
It is required that λ=hxC 8°ri (1) or less. Here, a blank constant:
h = 6.624XIOJ-see Speed of light: c
= 3. OX10'm/sec electronic port: 1
Since eV = 1.602 XIOJ, %3i02
Assuming that the energy gap is 8.9 eV, the wavelength of ultraviolet light: λ is (6) # 1.394 Xl0-' = 1394 A (angstroms) from equation (1).

イオン注入の作業中にシリコンウェーハに波Jk約14
00A以下の紫外線を照射すると、ゲート絶縁II〆を
形成する5i(hの導電性が高まり、ゲート電極に蓄積
された電荷はS10!膜を介してシリコンウェーハ11
に流れていくことになる。なお、ここでイオン注入中は
ディスク15は回転モータ16によって一様に回転し、
プロセスチャンバーは上下に運Qi111fろので、シ
リコンウェーハ]1には一様にイオン注入ケ紫外線照射
がなされろ。また、紫外線発生装置22は、例えば重水
素ランプてより構1i15することができろ。
Waves Jk approx. 14 on the silicon wafer during ion implantation work
When irradiated with ultraviolet rays of 00A or less, the conductivity of 5i(h) forming the gate insulation II increases, and the charges accumulated in the gate electrode are transferred to the silicon wafer 11 through the S10! film.
It will flow to Note that during ion implantation, the disk 15 is rotated uniformly by the rotary motor 16.
Since the process chamber is arranged vertically, the silicon wafer 1 is uniformly implanted with ions and irradiated with ultraviolet rays. Further, the ultraviolet ray generator 22 may be constructed from a deuterium lamp, for example.

〔発明の効果〕〔Effect of the invention〕

上記の如く本発明によれば、シリコンウェーハへのイオ
ン注入において、ゲート絶縁膜を構1yする51(hに
エネルギーが8.9eVl駁上の紫外線?:IIα射す
ることによってその導電性を高めろことがでとるので、
イオン注入によってデー) ’It ’rli K 蓄
積17た正電荷をシリコンウェーハ本体に流すことによ
って収り除(ことのできるイオン注入装置を提供jろこ
とかできる。また、本発明は紫外線照射装置を設り゛ろ
という比較的簡単な手段によって実現し、大きな効果乞
あげることができるので、経済的にも従来装置に比べて
効率がよい。
As described above, according to the present invention, during ion implantation into a silicon wafer, the electrical conductivity of the gate insulating film can be increased by irradiating ultraviolet rays with an energy of 8.9 eVl to 51 (h) forming the gate insulating film. Because it is possible,
It is possible to provide an ion implantation device that allows the positive charges accumulated by ion implantation to be absorbed by flowing them into the silicon wafer body. This can be realized by a relatively simple means of installation, and a great effect can be achieved, so it is economically more efficient than conventional devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はシリコンウェーハへのイオン注入ヲ説明¥δ図
、第2図は従来装置の一構成例の構成図、第3図は第2
図に示す従来装置の拡大図、第4図は本発明の一実施例
の構成図、第5図はs玉とSingのエネルギーバンド
図であろC 1・・・シリコンウェーハ、3・・・ゲート絶縁膜、4
・・・デー)K極、21・・・開口部、22・・・紫外
線照射装置置。 出願人代理人  猪  股     清第1図 第2図 第4図
Fig. 1 is a diagram explaining ion implantation into a silicon wafer, Fig. 2 is a block diagram of an example of the configuration of a conventional device, and Fig. 3 is a diagram illustrating ion implantation into a silicon wafer.
4 is a block diagram of an embodiment of the present invention, and FIG. 5 is an energy band diagram of S ball and Sing. C1...Silicon wafer, 3...Gate Insulating film, 4
...day) K pole, 21...opening, 22...ultraviolet irradiation device. Applicant's agent Kiyoshi Inomata Figure 1 Figure 2 Figure 4

Claims (1)

【特許請求の範囲】 表面に二酸化シリコンからなるゲート絶縁膜を設けかつ
このゲート絶縁膜上にゲート′屯極ケ設けてなるシリコ
ンウェーハにイオンを注入し、ソース領域およびドレイ
ン領域を形成するイオン注入装置において。 前記イオン注入乞している間は前記ゲート絶縁膜に波長
が1400オングストローム以下の紫外線を照射する紫
外線照射装置を備えろことを特徴とするイオン注入装置
[Claims] Ion implantation in which ions are implanted into a silicon wafer having a gate insulating film made of silicon dioxide on the surface and a gate electrode formed on the gate insulating film to form a source region and a drain region. In the device. An ion implantation apparatus characterized in that an ultraviolet irradiation device is provided for irradiating the gate insulating film with ultraviolet rays having a wavelength of 1400 angstroms or less during the ion implantation.
JP19663982A 1982-11-09 1982-11-09 Ion implantation device Pending JPS5985858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19663982A JPS5985858A (en) 1982-11-09 1982-11-09 Ion implantation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19663982A JPS5985858A (en) 1982-11-09 1982-11-09 Ion implantation device

Publications (1)

Publication Number Publication Date
JPS5985858A true JPS5985858A (en) 1984-05-17

Family

ID=16361110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19663982A Pending JPS5985858A (en) 1982-11-09 1982-11-09 Ion implantation device

Country Status (1)

Country Link
JP (1) JPS5985858A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019114536A (en) * 2017-12-20 2019-07-11 ザ・スウォッチ・グループ・リサーチ・アンド・ディベロップメント・リミテッド Method for implanting ions on surface of object to be treated and installation for implementing this method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4914090A (en) * 1972-05-16 1974-02-07
JPS5489475A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Ion implanting method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4914090A (en) * 1972-05-16 1974-02-07
JPS5489475A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Ion implanting method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019114536A (en) * 2017-12-20 2019-07-11 ザ・スウォッチ・グループ・リサーチ・アンド・ディベロップメント・リミテッド Method for implanting ions on surface of object to be treated and installation for implementing this method

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