JPH03179653A - Apparatus for implanting ion - Google Patents

Abstract

PURPOSE:To easily control an amount of electrons to be radiated to a silicon substrate at the time of ion implantation and prevent charge-up by providing a bias power source on a sample mount. CONSTITUTION:An electron generating apparatus 3 for neutralizing a positive charge made incident to a semiconductor substrate 2 at the time of ion implantation and a bias electrode 8 for applying bias to a sample mount 1 for holding the semiconductor substrate 2 are provided. In this case if potential of the sample mount 1 of the ion implantation is negatively biased, incidence of electrons is prevented so that neutralization of the positive charge made incident to the silicon substrate 2 can be easily controlled. Thus charge-up at the time of ion implantation of high dose can be suppressed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to an ion implantation device.

2. Description of the Related Art Conventionally, this type of ion implantation apparatus has had a configuration as shown in FIG. In FIG. 2, 1 is a sample stage, and 2 is a silicon substrate fi placed on the sample stage 1. 3 is a primary electron gun for emitting electrons, and the primary electrons 4 emitted from the primary electron gun 3 collide with a target 5 to emit secondary electrons 6, which are irradiated onto the silicon substrate 2. . 7 is an ion beam of ions to be implanted, usually As+B
F2'', B'', P'', etc. are used to form an impurity layer on the silicon substrate 2. However, when the ion dose exceeds I x 10''ca-'', a positive charge is generated on the silicon substrate 2. The impurities are implanted and charged up, which deteriorates the uniformity of the dose of impurities.Therefore, in order to improve the uniformity of the dose, secondary electrons 6 are introduced into the silicon substrate 2 for the purpose of neutralizing the positive charge. It is irradiating.

Also, when implanting the source and drain regions of an n-channel MOS transistor, the gate! As4 at 40KeV with Selfa line using the pole as a mask,
5xlo15,. The injection was performed at a dose of , , /d and a secondary electron current of 1.5 mA. In this case, secondary electrons are irradiated for the purpose of improving the uniformity of the ion-implanted layer and preventing destruction of the gate oxide film.

, Problem to be Solved by the Invention In such a configuration, the energy distribution of secondary electrons is O
~100eV, the silicon substrate will be charged up to minus t(ff) by irradiation with secondary electrons.In practice, controlling the current value of secondary electrons will not sufficiently prevent charge-up. It is difficult to reduce the charge to a low level, and there is a problem in that this charge-up destroys the gate oxide film of the MOS transistor.

The present invention solves these problems, and aims to provide an ion implantation device that can easily control the amount of electrons irradiated onto a silicon substrate during ion implantation and can reduce charge-up by 1. It is something to do.

Means for Solving the Problems In order to solve the above-mentioned conventional problems, the ion implantation apparatus of the present invention provides a bias power supply on the sample stage, controls the potential of the sample stage, and prevents charge-up due to excessive electrons. It has grown into something like this.

Effect: Due to this elliptical principle, if the potential of the sample stage during ion implantation is biased negatively, the incidence of electrons will be reduced, making it easy to control the neutralization of positive charges incident on the silicon substrate. can.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a sectional view of an ion implantation apparatus according to an embodiment of the present invention. In Figure 1, 1 is a sample stage, 2 is a silicon substrate, 3 is a primary electron gun for emitting electrons, 4 is a primary electron emitted from the primary electron gun 3, 5 is a target, and 6 is a target. Secondary electrons emitted from 5 and ion beam 7 are the same as those shown in FIG. Reference numeral 8 denotes a bias power supply for applying a bias to the sample stage 1.

Next, ion implantation for forming source/drain diffusion regions of an N-channel MOS transistor will be explained. First, 200 to 1
After growing a gate oxide film of 000A, a polysilicon film is grown. After etching the gate tS with the resist master, the resist is removed. Next, A, 4 ions are accelerated to an energy of 50 eν, 5X1G@1°□/1.
Ion implantation is performed under the condition that the current value of secondary electrons is 15 capes. At this time, charge-up due to excessive electrons can be suppressed by controlling the bias power supply 8 to -5 to -15V. That is, when the voltage of the bias power supply 8 = OV, the potential difference applied between the electrode of the MOS transistor and the substrate is about 15V, so by setting the bias voltage to -5 to -15V, the potential difference applied to the gate oxide film is reduced. Therefore, the gate oxide film of the MOS transistor is destroyed on the surface 111102,
Even when the oxide IIA thickness is 200 A, it almost disappears.

Effects of the Invention As described above, according to the present invention, it is possible to suppress charge-up during high-dose ion implantation, and to eliminate damage to the gate oxide film caused by this.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an ion implantation device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional ion implantation device. DESCRIPTION OF SYMBOLS 1... Sample stage, 2... Silicon substrate, 3... Primary electron gun, 4... Primary electron, 5... Target, 6
...Secondary electron, 7...Ion beam, 8...Bias power supply.

Claims (1)

[Claims] 1. An ion implantation device equipped with an electron generator for neutralizing positive charges incident on a semiconductor substrate during ion implantation and a bias power supply for applying a bias to a sample stage for holding the semiconductor substrate. .