JP2616423B2 - Ion implanter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implanter having a charge neutralizing mechanism for preventing a semiconductor substrate from being charged.

[0002]

2. Description of the Related Art FIG. 6 is a schematic view of a conventional ion implanter having a charge neutralizing mechanism (Japanese Patent Laid-Open No. 63-4024).
3). This is an ion implanter having a negative potential electrode type charge neutralizer. In FIG. 6, reference numeral (7) denotes a semiconductor substrate mounted on a metal substrate holder (8) grounded via an ammeter (16), and a positive charge ( Accelerated ions having (+) are implanted into the surface of the semiconductor substrate (7) while scanning. In the substrate holder (8), a substrate holder (8) and a semiconductor made of aluminum or carbon, which surround the periphery of the semiconductor substrate (7) and have substantially the same height as the surface of the semiconductor substrate (7). An insulating ring (12) insulated from the substrate (7) is provided. A high input impedance electrometer (15) is connected between the insulating ring (12) and the substrate holder (8), and the potential between the insulating ring (12) and the substrate holder (8) is adjusted. It can be measured. This electrometer (1
According to 5), the state of the potential of the insulating ring (12) corresponding to the potential of the surface of the semiconductor substrate (7) is grasped, and the control device (1)
According to 4), the voltage applied to the negative potential electrode (6), which is an electron supply source, is controlled to change the amount of secondary electrons emitted from the negative potential electrode (6), thereby changing the amount of secondary electrons on the surface of the semiconductor substrate (7). The potential is set to zero. (10) in this figure is a mask,
(11) is a suppressor, and (13) is a Faraday cup.

[0003]

In the conventional method, a potential corresponding to the surface of the semiconductor substrate (7) is monitored by an insulating ring (12) and electrons for neutralization corresponding to the potential are supplied. The potential on the surface of the semiconductor substrate (7) is set to zero. The ion beam supplied with the electrons for neutralization has a shape in which the electrons are surrounded around the ion beam as shown in FIGS. Therefore, the potential of the surface of the semiconductor substrate changes as shown in FIG. 8 when the ion beam supplied with the electrons passes therethrough. That is, they are first exposed to electrons and have a negative potential. Next, it is exposed to the ion beam, changes from a negative potential to a positive potential, and finally is again exposed to electrons to a zero potential. When the beam current increases for higher throughput, the potential change on the Si substrate surface shown in FIG. 8 increases. Therefore, while this large potential change occurs many times due to repeated scanning during ion implantation, problems such as dielectric breakdown of the gate oxide film occur.

[0004]

SUMMARY OF THE INVENTION An ion implantation apparatus according to the present invention solves the above-mentioned problems. In an ion implantation apparatus having a charge neutralizing mechanism, a mechanism for emitting a plurality of ion beams at predetermined intervals is provided. Wherein the mechanism for emitting a plurality of ion beams having the predetermined interval is for splitting the ion beam to form a plurality of ion beams, and the mechanism for splitting the ion beam is provided with a positively biased core. It is characterized by being a meter.

[0005]

In the present invention, the mechanism for emitting a plurality of ion beams is to split the ion beam to form a plurality of ion beams, and the mechanism for splitting the ion beam is a collimator to which a positive bias is applied. By implanting with a plurality of ion beams, the beam current value of each beam can be reduced as compared with the case of implanting with one ion beam. Therefore, a change in potential on the semiconductor substrate when the ion beam passes over the semiconductor substrate can be reduced, and problems such as dielectric breakdown of the gate oxide film can be prevented.

First, a reference example will be described with reference to the drawings. FIG. 1 is a schematic view of an ion implantation apparatus having a charge neutralization mechanism as a reference example. As shown in FIG. 1, in this ion implantation apparatus, a semiconductor substrate (7) is placed on a metal substrate holder (8) that is grounded via an ammeter (16), and has a beam shape. Focused accelerating ions having positive charges (+) are injected into the surface of the semiconductor substrate (7) while scanning. In the substrate holder (8), a substrate holder (8) and a semiconductor made of aluminum or carbon, which surround the periphery of the semiconductor substrate (7) and have substantially the same height as the surface of the semiconductor substrate (7). An insulating ring (12) insulated from the substrate (7) is provided. A high input impedance electrometer (15) is connected between the insulating ring (12) and the substrate holder (8), and the potential between the insulating ring (12) and the substrate holder (8) is adjusted. It can be measured. By means of the electrometer (15), an insulating ring (12) corresponding to the potential of the surface of the semiconductor substrate (7)
The state of the potential of the electron is grasped, and the voltage applied to the negative potential electrode (6), which is an electron supply source, is controlled by the controller (14) to control the amount of secondary electrons emitted from the negative potential electrode (6). Is changed to zero the potential on the surface of the semiconductor substrate (7).

The apparatus of the reference example shown in FIG. 1 has a grounded collimator (9) installed in front of a mask (10).
In this figure, (11) is a suppressor, and (13) is a Faraday cup. FIG. 2 shows a plan view of the collimator (9). Circular holes with a diameter of 4 mm are arranged in a grid at intervals of 5 cm. The thickness of the collimator (9) is 5 cm. The distance from the substrate to the collimator (9) is 20 cm. The incident ion beam is split into a plurality of ion beams by the collimator (9), and then injected into the semiconductor substrate (7) together with the electrons supplied from the electron supply source (6). The beam that has passed through the collimator (9) is not only a perfectly linear component, but also has an aspect ratio of 12.5 through the collimator (9). It becomes an ion beam of 3.6 cm.
The ion beam reaching the semiconductor substrate (7) is shown in FIG.
The shape is as follows. FIG. 3A is a plan view of the beam, and FIG. 3B is a cross-sectional view taken along a line AB in FIG.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a schematic view of an ion implantation apparatus having a charge neutralizing mechanism according to an embodiment of the present invention. In the embodiment shown in FIG. 5 of the present invention, the mask (1
A collimator (9) is installed in front of 0), and the ion beam is split and implanted. The size and arrangement of the circular hole of the collimator (9), the thickness of the collimator (9), and the distance from the substrate to the collimator (9) are the same as those in the above reference example. The collimator (9) is at a positive potential as shown in FIG. 5, and the mechanism for splitting the ion beam applies a positive bias. The incoming ions repel the collimator (9) because the collimator (9) is at a positive potential, and take an orbit that avoids the collimator (9). Therefore, when a positive bias is not applied to the collimator (9), some of the ions that have collided with the collimator (9) avoid the collimator (9) and pass through the collimator (9). Part can be passed. Therefore, in the present invention, the amount of ions lost in the collimator (9) can be reduced as compared with the reference example.

In order to form the source and drain of an N-channel transistor, A
s acceleration energy 60 KeV, dose 3E15cm
^-2 , implantation was performed under the condition of a beam current of 25 mA according to the conventional technique and the example of the present invention. In the case of the present invention, the injection was performed with the total current value of each divided beam being 25 mA. In the case of performing the implantation according to the conventional technique, 15% of the dielectric breakdown of the gate oxide film occurred, but in the case of performing the implantation according to the present invention, there was no dielectric breakdown.

Since the ion implantation is performed by using a plurality of ion beams as described above, when the implantation is performed at the same throughput as the conventional one, the beam current for each one is the same as the beam current when the conventional single beam is implanted. The value may be a value obtained by dividing by the number of divisions. It is conventionally known that the amount of potential change on the surface of a semiconductor substrate when an ion beam passes increases depending on the beam current.However, in the present invention, when implanting at the same throughput, Therefore, as shown in FIG. 4, the amount of potential change on the surface of the semiconductor substrate (7) when the ion beam passes is small, as shown in FIG. Therefore, it is possible to prevent the problem such as the dielectric breakdown of the gate oxide film caused by the conventional large potential change.

[0011]

As described above, according to the present invention, the mechanism for emitting a plurality of ion beams having a predetermined interval is to split the ion beam to form a plurality of ion beams. Injects a plurality of ion beams with a collimator to which a positive bias is applied, so that the current value of each beam is lower than that of a single ion beam, and the ion beam passes over the semiconductor substrate. In this case, the potential change on the semiconductor substrate at the time of this is reduced. Therefore, it is possible to prevent a problem such as a dielectric breakdown of the gate oxide film.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a reference example.

FIG. 2 is a plan view of a collimator of a reference example.

FIG. 3 is a diagram showing an ion beam shape when reaching a semiconductor substrate of a reference example;

FIG. 4 is a diagram showing a potential change on the surface of the semiconductor substrate when the ion beam passes over the semiconductor substrate.

FIG. 5 is a schematic view of an embodiment of the present invention.

FIG. 6 is a schematic view of a conventional example.

FIG. 7 is a diagram showing an ion beam shape when the ion beam reaches a semiconductor substrate in a conventional example.

FIG. 8 is a diagram showing a potential change on the surface of a semiconductor substrate when an ion beam passes over the semiconductor substrate in a conventional example.

[Explanation of symbols]

 Reference Signs List 6 electron supply source 7 semiconductor substrate 8 substrate holder 9 collimator 10 mask 11 suppressor 12 insulating ring 13 Faraday cup 14 control device 15 electrometer 16 ammeter

Claims (1)

(57) [Claims] 1. An ion implanter having a charge neutralizing mechanism, comprising: a mechanism for emitting a plurality of ion beams having a predetermined interval, wherein the mechanism for emitting a plurality of ion beams having the predetermined interval is an ion beam. Wherein a plurality of ion beams are formed by dividing the ion beam, and the mechanism for dividing the ion beam is a collimator to which a positive bias is applied.