JPH05175152A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide an ion implanting method by which the occurrence of charge-up phenomena on the surface of a semiconductor substrate can be reduced at the time of implanting ions into the substrate in a semiconductor manufacturing process. CONSTITUTION:The title manufacturing method includes a process for forming openings 3 through a resist film 2 in the ion implanting areas of the substrate 1 after coating the substrate 1 with the film 2, process for performing first-stage implantation of impurity ions 4 into the substrate 1 by using the film 2 as a mask, with the beam current used for the implantation being reduced in amount from that of a prescribed beam current used for forming a diffusion layer, process for performing second-stage ion implantation of the impurity ions 4 into the substrate 1 by using the prescribed beam current for forming the diffusion layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation method in a semiconductor manufacturing process, and more particularly to reducing a charge-up phenomenon on a semiconductor substrate surface during ion implantation.

In recent years, in order to reduce charge-up at the time of ion implantation, it has been required to electrically neutralize charges accumulated on the resist film surface of a semiconductor substrate, that is, positive charges.

Therefore, a negative charge (electron) is created,
It is necessary to force neutralization.

[0004]

2. Description of the Related Art FIG. 3 is an explanatory view showing a beam path diagram of an ion implantation apparatus. In the figure, 11 is an ion source, 12
Is a beam extraction part, 13 is a beam acceleration part, 14 is an analyzer magnet, 15 is a scan, 16 is an angle collector, 17 is an electron generator, 18 is a filament, 19 is a reflector, 20 is a Faraday cup, 21 is a beam gate, 22 is a substrate, 23 is a desk, and 24 is a rotation axis.

Conventionally, as a method of reducing the charge-up phenomenon, as shown in the beam path diagram of the ion implantation apparatus of FIG. 3, an electron generator 17 is provided in the path of the ion beam just before the semiconductor substrate 22, and tungsten ( W) and molybdenum (M
The filament 18 made of o) is heated to generate electrons, which are scattered by the reflector 19 made of aluminum (Al) or the like and are incident on the semiconductor substrate 22 and the surface of the resist film or the like on the semiconductor substrate 22. It was carrying out the forced neutralization by the electron of the + charge which was charged to.

However, when electrons are generated, a metallic substance such as W or Mo forming the filament 18 of the electron generator 17, that is, a contaminant to the semiconductor substrate 22 is also ionized at the same time. Occurs.

[0007]

Therefore, many pollutants adhere to the surface of the semiconductor substrate, causing a problem of metal contamination of the semiconductor substrate.

In view of the above points, it is an object of the present invention to eliminate metal contamination of a semiconductor substrate and reduce the charge-up phenomenon.

[0009]

FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a resist film, 3 is an opening, 4 is an impurity ion, 5 is a field oxide film, 6 is a gate oxide film, 7 is a gate electrode, 8 is a sidewall, 9 is an LDD layer, Reference numeral 10 is a source / drain layer.

As a means for solving the above problems, it is preferable to increase the beam current, which is the cause of the charge-up phenomenon, in steps rather than immediately. Therefore, when ion implantation is performed, the beam current is increased in two steps.

In the first step, the beam current is lowered so that + charge is not accumulated on the surface of the resist film, the surface of the resist film is gradually carbonized, and the conductivity is increased. next,
In the second step, the beam current is made normal and the necessary amount of ions is injected.

That is, the object of the present invention is to coat a semiconductor substrate 1 with a resist film 2 as shown in FIG.
The resist film 2 is formed on the ion implantation region of the semiconductor substrate 1.
The step of forming the opening 3 of the semiconductor substrate 1 and the semiconductor substrate 1 using the resist film 2 as a mask as shown in FIG.
Impurity ions 4 are made less than the beam current for forming the diffusion layer, and the first step of implanting is performed. Next, as shown in FIG. 1C, the resist film 2 is used as a mask. In order to form the diffusion layer of the impurity ions 4 in the semiconductor substrate 1, the step of increasing the beam current from the first step and performing the implantation of the second step is achieved.

[0013]

According to the present invention, as described above, the surface of the resist film is carbonized in one step of ion implantation to improve the conductivity, and the charges to be accumulated by the ions implanted in two steps are grounded. ， Reduce charge-up.

Further, according to the present invention, the electron generator is not required, so that the metal contamination of the semiconductor can be eliminated and the charge-up phenomenon can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic cross-sectional view of the principle of the present invention and steps in one embodiment, and FIG. 2 is a yield distribution diagram of oxide film breakdown characteristics in the present invention and a conventional example.

An embodiment of the present invention will be described with reference to FIG. The yield under the conditions of the present invention is shown in FIG. 2C. As shown in FIG. 1A, the MOS transistor L
A resist film 2 serving as a mask for ion implantation is applied on a semiconductor substrate 1 made of a Si wafer having a DD layer formed thereon by a Sbinner to a thickness of 8,000Å.

The resist film 2 is patterned by photolithography to form openings 3 in the source / drain formation regions of the semiconductor substrate 1. As shown in FIG. 1B, using the resist film as a mask, as impurity ions 4 in the formation region of the source / drain layer 10 of the semiconductor substrate 1,
Arsenic ions (As ⁺ ) are used as the first step of ion implantation, the beam current is 300 μA, the acceleration voltage is 70 KeV, and the dose is 2x.
Implant at 10 ¹⁵ / cm ² to carbonize the surface of the resist film.

After that, as shown in FIG.
⁺ , Beam current 3.0 mA, accelerating voltage 70 KeV, dose 2x1
Implantation at 0 ¹⁵ / cm ² and heat treatment at 1,050 ℃ for 30 seconds in a nitrogen (N ₂ ) atmosphere to activate As ⁺ ,
Form 10.

For comparison, a conventional method is used, that is, As ^{+ is used} with a beam current of 3.0 mA, an acceleration voltage of 70 KeV, and a dose of 4 × 10 ¹⁵ / cm ^2.
When the source / drain layers are formed by implanting (Fig. 2
D), and the characteristic yield of oxide film destruction when two-step ion implantation was performed under the intermediate condition between the conventional example and the present invention (FIGS. 2A and 2B).

As a result, comparing the characteristic yields, as shown in FIG. 2, the yield of the oxide film destruction of the MOS transistor on the tested semiconductor substrate is 8 in the conventional example (FIG. 2D).
In the present invention (Fig. 2C), the yield was ~ 25%.
The yield was 55% to 95%, and the yield was improved 4 to 5 times.

Also, in the investigation of metal contamination of MOS devices such as W and Mo, the metals of W and Mo, which were detected in trace amounts by the conventional method, were not detected by the method of the present invention.

[0022]

According to the present invention, as described above,
It has the effects of eliminating metal contamination and reducing the charge-up phenomenon.

Further, since the electron generator is not provided, the negative charge-up phenomenon does not occur, which greatly contributes to the device quality and the yield improvement.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a yield distribution diagram of oxide film breakdown characteristics in the present invention and a conventional example.

[Fig. 3] Beam path diagram of the ion implanter

[Explanation of symbols]

 1 Semiconductor Substrate 2 Resist Film 3 Opening 4 Impurity Ion 5 Field Oxide 6 Gate Oxide 7 Gate Electrode 8 Sidewall 9 LDD Layer 10 Source / Drain Layer 11 Ion Source 12 Beam Extraction 13 Beam Accelerator 14 Analyzer Magnet 15 Scan 16 Angle collector 17 Electron generator 18 Filament 19 Reflector 20 Faraday cup 21 Beam gate 22 Substrate 23 Desk 24 Rotation axis

Claims (1)

[Claims] 1. A process of coating a resist film (2) on a semiconductor substrate (1) and forming an opening (3) of the resist film (2) on an ion implantation region of the semiconductor substrate (1). And a step of performing the first step implantation by using the resist film (2) as a mask to reduce the amount of impurity ions (4) in the semiconductor substrate (1) below a predetermined beam current for forming a diffusion layer. Then, using the resist film (2) as a mask, the semiconductor substrate
(1) A step of implanting the impurity ions (4) in the second step with the predetermined beam current for forming a diffusion layer in the semiconductor device manufacturing method.