JP3410946B2 - Ion implantation apparatus and method of manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation apparatus, and more particularly to a technique for suppressing charging (charge-up) in a product wafer during ion implantation. The present invention also relates to a method of manufacturing a semiconductor device using this ion implantation device.

[0002]

2. Description of the Related Art Conventionally, as an example of an ion implantation apparatus, a plurality of product wafers 2 are integrally formed with a locus passing through an irradiation range of an ion beam 1 as shown in a greatly simplified manner in FIG. In addition, there is a wafer processing chamber (not shown) for performing ion implantation into each of the product wafers 2 while rotating at a high speed of about 2000 rpm. Wafer wheel 5 provided with a plurality of wafer holders 4 for radially holding the product wafers 2 and extending radially from the wafer wheel 3.
Is provided. The rotating shaft 3 here is grounded, and the ion beam 1 is applied to the entire surface of the product wafer 2 by scanning the rotating shaft 3 while rotating the wafer wheel 5.

[0003]

By the way, in the conventional ion implanter, the following problems would occur. That is, although not shown, when the surface of the product wafer 2 to be ion-implanted is covered with an insulating film such as a silicon oxide film, charge-up at the time of ion implantation occurs, that is, the insulation Positive charges will be accumulated near the surface of the film, and if the amount of positive charges accumulated exceeds the breakdown voltage of the insulating film, dielectric breakdown will occur. Although not shown in the drawings in order to avoid such inconvenience, in the prior art, as disclosed in Japanese Patent Laid-Open No. 63-207126, the surface of each product wafer 2 is not shown. On the other hand, a metal film for shielding made of aluminum or the like is formed, ion implantation is performed, and then the metal film is entirely removed.

However, if such a conventional technique is adopted, the shield metal film must be purposely formed and then removed, which requires extra labor and cost in these steps. Will end up. Also,
Not only may the insulating film be damaged when the metal film is removed, but aluminum that forms the metal film may enter the silicon product wafer 2 or the bonding portion. As a result, the device characteristics are deteriorated due to the formation of energy levels due to metal contamination.

After the ion implantation, an electromagnetic wave having a charge having a polarity opposite to that of the charge accumulated on the surface of the product wafer 2 is irradiated to neutralize electrically. That is, in the above example, since positive charges are accumulated on the surface of the product wafer 2, it is possible to prevent charge-up by irradiating electrons of the opposite polarity to electrically neutralize them. .

However, in this charge neutralization method, in addition to the addition of new steps and devices, the electron irradiation dose must be set in accordance with the accumulated charge amount on the surface of the product wafer 2. Therefore, optimization is difficult, and proper neutralization is not always performed.

The charge accumulation on the surface of the product wafer as described above is caused as in the case of forming the source and drain regions of the semiconductor device, especially the MOS type semiconductor device having the extension structure.
This is conspicuous when ions are implanted in a substrate at a high concentration, and an effective improvement measure is desired.

The present invention was devised in view of these inconveniences, and despite the fact that it is not necessary to form or remove a shielding metal film on the surface of a product wafer, An object of the present invention is to provide an ion implantation device that can easily suppress charge-up during ion implantation, although it is not necessary to irradiate electromagnetic waves to electrically neutralize it. At the same time, semiconductor devices, especially M
An object of the present invention is to provide a method for performing ion implantation without causing charge-up in a manufacturing process of an OS semiconductor device.

[0009]

SUMMARY OF THE INVENTION An ion implantation apparatus according to the present invention performs ion implantation on each product wafer while integrally rotating a plurality of product wafers at a high speed along a locus passing through an irradiation range of an ion beam. The wafer wheel is equipped with a wafer processing chamber for execution, and has a plurality of wafer holders that radially extend from the rotation axis and hold each of the product wafers. And then placed on the wafer holder
Held or integrated by a conductive plate-shaped member,
Or a conductive rod-shaped member placed between the wafer holders
Preferably, a linear member is arranged. When such a configuration is adopted, the conductive plate-shaped member, rod-shaped member or linear member is rotating at a high speed on the same trajectory as the product wafer to be charged up during ion implantation, and the product is A conductive plate-shaped part similar to a wafer
As a result of the material, rod-shaped member, or linear member passing through the irradiation range of the ion beam, the electric charge of the spatial electromagnetic field generated as the product wafer is charged up is a conductive plate-shaped portion.
It will be absorbed by the material, the rod-shaped member or the linear member , and the charge-up at the time of ion implantation in the product wafer will not be so high that it exceeds the withstand voltage of the insulating film.

A method of manufacturing a semiconductor device according to the present invention uses the above-mentioned ion implantation to manufacture a semiconductor device, especially M
The method is characterized by including a step of performing ion implantation for forming source and drain regions of an OS type semiconductor device and / or a step of performing ion implantation into a gate electrode. Further, according to this method, it is possible to perform higher-concentration ion implantation without causing dielectric breakdown of the gate insulating film when forming the source region and the drain region of the MOS semiconductor device or when forming the gate electrode. Becomes

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The ion implantation apparatus according to claim 1 of the present invention is one in which a plurality of product wafers are integrally rotated at a high speed along a locus passing through an irradiation range of an ion beam, and ions are applied to each product wafer. An ion implantation apparatus having a wafer processing chamber for performing implantation, which is grounded on a wafer wheel having a plurality of wafer holders radially extending from a rotation axis to hold each of product wafers. It passes through the irradiation range of the ion beam, Katsuu
Placed on a wafer holder and held or integrated guide
It is characterized in that an electrically conductive plate member is provided. The ion implantation apparatus according to claim 2 is an ion beam
A number of product wafers can be
For each product wafer while rotating the c integrally at high speed
Ion Injection with Wafer Processing Chamber for Performing Ion Implantation
Input device, which extends radially from the rotating shaft
Equipped with multiple wafer holders to hold each wafer
The wafer wheel is grounded and then ion beamed.
Is passed between the wafer holders and is placed between the wafer holders.
Conductive rod-like member or a linear member is characterized that you have been provided.

[0012]

Further, according to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the ion implantation apparatus according to the first or second aspect is used to perform ion implantation for forming a source / drain region of a MOS semiconductor. The method is characterized by including a step of implanting ions into the gate electrode.

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is an explanatory view showing a greatly simplified internal structure of a wafer processing chamber provided in an ion implantation apparatus according to the first embodiment of the present invention. Since the internal structure of the wafer processing chamber is basically the same as that of the conventional structure, parts and portions in FIG. 1 that are the same as those in FIG. 3 are given the same reference numerals.

In the ion implantation apparatus according to the first embodiment, a plurality of product wafers 2 are integrally formed along a locus passing through the irradiation range of the ion beam 1 as in the conventional embodiment.
In addition, a wafer processing chamber (not shown) for performing ion implantation into each product wafer 2 while rotating at a high speed of about 2000 rpm is provided.
In the wafer processing chamber, a rotary shaft 3 that scans the product wafer 2 along the irradiation range of the ion beam 1 while rotating, and the product wafer 2 radially extended from the rotary shaft 3 respectively. A wafer wheel 5 including a plurality of wafer holders 4 for holding the wafer is provided. The rotary shaft 3 that constitutes the wafer wheel 5 is grounded, and each of the wafer holders 4 is also grounded via the rotary shaft 3.

In the ion implantation apparatus according to this embodiment, the plate-like member 6 which is electrically grounded and passes through the irradiation range of the ion beam 1 is arranged on the wafer wheel 5. it is characterized in, specifically, if example embodiment, the silicon surface is made to those N-type silicon substrate became like exposed is held is placed on the wafer holder 4. That is, the ion implantation apparatus is different from the conventional one in that some of the plurality of wafer holders 4 on which a plurality of product wafers 2 are mounted and held, and at least one of the wafer holders 4 has a conductive property. Of the plate-shaped member 6 held by the wafer holder 4, since each wafer holder 4 is grounded via the rotating shaft 3 at this time, each of the plate-shaped members 6 held by the wafer holder 4 is also held. It is grounded.

Further, in the present embodiment, the plate member 6 may be formed integrally with the wafer holder 4, and specifically, the plate member 6 may be previously integrated on some of the wafer holders 4 by adhesion or the like. It can also be turned into.

By the way, an N-type silicon substrate (hereinafter referred to as a sample substrate C) in which the silicon surface is exposed or a silicon substrate whose entire surface is covered with a 330-nm-thick polycrystalline silicon film doped with N-type impurities ( Hereinafter, a sample substrate D) is prepared as a dummy wafer corresponding to the conductive plate-like member 6, and for comparison, a silicon substrate whose entire surface is covered with an insulating silicon oxide film having a film thickness of 500 nm ( Hereinafter, a sample substrate A) and a silicon substrate whose entire surface is covered with a photoresist film having a film thickness of 1.5 μm (hereinafter referred to as sample substrate B) are prepared as dummy wafers whose surfaces are insulators. As shown in FIG.
I tried an ion implantation experiment after placing it on top and holding it. In FIG. 1, the total number of wafer holders 4 is 6, but in this experiment, the total number of wafer holders 4 is 25.

Further, in this ion implantation experiment, a gate leak current value measurement silicon substrate for evaluating damage due to charge-up (hereinafter referred to as an evaluation substrate), that is, a gate oxide film (film thickness 8 nm) is formed on the gate. An evaluation substrate formed with electrodes (N-type polysilicon: film thickness 330 nm) is held by one of the wafer holders 4, while the same type of sample substrates A to D is held by another wafer holder 4 ( (In actuality, 24 ions are held), and the ion implantation is performed, and in the damage evaluation of the sample substrates A to D, the gate leak in the evaluation substrate simultaneously processed with each of the sample substrates A to D is performed. from the measurement results of current values, the electric field of the gate oxide film at the time of the criteria and the gate leakage current density of 0.1 mA / cm ² is 10 MV / cm or less If it assumed to be good, and,
The number of non-defective products out of 100 chips is evaluated as a yield rate.

In this ion implantation experiment,
Using PI-9500 manufactured by AMT as an ion implanter, BF ₂ ⁺ is implanted with an acceleration energy of 40 KeV while rotating the wafer wheel 5 at a high speed of about 2000 rpm. The value is set to 10 mA.

Further, in this ion implantation experiment, a gate leak current value measurement silicon substrate for evaluating damage due to charge-up (hereinafter referred to as an evaluation substrate), that is, a gate oxide film (film thickness 8 nm) is formed on the gate. An evaluation substrate formed with electrodes (N-type polysilicon: film thickness 330 nm) is held by one of the wafer holders 4, while the same type of sample substrates A to D is held by another wafer holder 4 ( (In actuality, 24 ions are held), and the ion implantation is performed, and in the damage evaluation of the sample substrates A to D, the gate leak in the evaluation substrate simultaneously processed with each of the sample substrates A to D is performed. from the measurement results of current values, the electric field of the gate oxide film at the time of the criteria and the gate leakage current density of 0.1 mA / cm ² is 10 MV / cm or less If it assumed to be good, and,
The number of non-defective products out of 100 chips is evaluated as a yield rate.

According to the damage evaluation based on such an ion implantation experiment, the dummy wafers when the antenna ratios of the gate electrodes on the evaluation substrate are both 1: 2000 are the sample substrates D, C, B and A. It is clear that the yield decreases to 100%, 90%, 70%, and 20% according to the order of, and compared with the case where the sample substrate A or the sample substrate B corresponding to the product wafer 2 is a dummy wafer, the dummy wafer It has been confirmed that the charge-up of the evaluation substrate is significantly reduced and the damage is reduced when the sample substrate C or the sample substrate D has conductivity. It is considered that such experimental results are obtained because the more conductive the dummy wafer is, the less likely it is that charge-up will occur in each of the dummy wafers rotating at high speed.

Further, an attempt was made to compare with the charge neutralization method.
That is, a silicon substrate (hereinafter referred to as a sample substrate E) whose entire surface is covered with an insulating silicon oxide film having a film thickness of 660 nm (hereinafter referred to as a sample substrate E) or a silicon substrate whose entire surface is covered with a photoresist film having a film thickness of 1.5 μm ( Hereinafter, referred to as a sample substrate F), an N-type silicon substrate having a bare silicon surface (hereinafter referred to as a sample substrate G), and a 330 nm-thick polycrystalline silicon film doped with an N-type impurity were used to cover the entire surface. A silicon substrate (hereinafter referred to as a sample substrate H) was prepared as a dummy wafer, and each of these dummy wafers was placed and held on the wafer holder 4 and an ion implantation experiment was performed. In this ion implantation experiment, A
Using PT-9500 manufactured by MT, while rotating the wafer wheel 5 at a high speed of about 2000 rpm, BF ₂ ^{+ is set} to 4
Injection is performed with an acceleration energy of 0 KeV, and the beam current value at this time is set to 10 mA.

Then, in order to evaluate damage due to charge-up, one of the wafer holders 4 holds an evaluation substrate having the same structure as described above, while the sample substrate E is held.
~ H of the same type is held in another wafer holder 4 (actually 24 pieces), and then ion implantation is performed. At that time, a plasma flood system (PFS) is used during the ion implantation. A comparison was made at the same time between when not used (OFF) and when used (ON). Sample substrate E ~
In the damage evaluation of H, the judgment standard is 0.1 mA / cm from the measurement result of the gate leak current value in the evaluation substrates simultaneously processed with each of the sample substrates E to H.
When the electric field of the gate oxide film is 10 MV / cm or more when the gate leakage current density is set to ² , it is considered to be a good product,
In addition, the number of non-defective products out of 100 chips is evaluated as the yield rate. In addition, the above experiment was carried out by using an evaluation substrate with an antenna ratio of the gate electrode and the wiring portion of 1000
2000, 3000, 4000 and 6000 were used. The results are shown in Table 1.

[0026]

[Table 1]

From Table 1, the sample substrates G and H when PFS is OFF have a higher yield than the sample substrates E and F, and are higher than the sample substrates G and H when PFS is ON.
It can be seen that the use of a conductive dummy wafer can more effectively suppress the occurrence of charge-up, as compared with the charge neutralization method that also uses PFS.

In this way, among the plurality of wafer holders 4 on which the plurality of product wafers 2 are mounted and held, at least one or more of the wafer holders 4 are provided with conductive plate-like members 6. When a certain silicon substrate, that is, a silicon substrate whose entire surface is covered with an impurity-doped polycrystalline silicon film is placed and held, ion implantation is performed, and product wafer 2 is charged up at the time of ion implantation Like the product wafer 2, the plate-shaped member 6 having conductivity is rotating at a high speed on the same locus as the plate-shaped member 6
Will pass through the irradiation range of the ion beam 1. Then, in this case, the charge in the space electromagnetic field induced by the charge-up of the product wafer 2 and the electrons generated from the plate-like member 6 is conducted between the product wafer 2 and the plate-like member 6. In the vicinity of the locus, a conductive ring-shaped conductive state occurs. As a result, the charge-up at the time of ion implantation in the product wafer 2 is suppressed after passing through such a conduction state,
The charge up of the product wafer 2 will not increase so much that it exceeds the withstand voltage of the insulating film. In this case, the plate-like member 6 having conductivity does not necessarily have to be the silicon substrate, and it goes without saying that it may be a metal plate coated with carbon or silicon carbide.

(Embodiment 2) In Embodiment 1, the plate-like member 6 having conductivity is placed and held on some of the wafer holders 4, but it is limited to such a structure. However, it is also possible to adopt the configuration shown in FIG. That is, FIG. 2 is an explanatory view showing a greatly simplified internal structure of the wafer processing chamber included in the ion implantation apparatus according to the second embodiment of the present invention. The internal structure of the wafer processing chamber according to the second embodiment is as follows. Since it is basically the same as that of the first embodiment, parts and portions in FIG. 2 that are the same as those in FIG. 1 are given the same reference numerals.

The ion implantation apparatus according to the second embodiment performs ion implantation on each of the product wafers 2 while integrally rotating the plurality of product wafers 2 at a high speed along a locus passing through the irradiation range of the ion beam 1. A wafer processing chamber (not shown) for execution is provided, and in the wafer processing chamber, a rotating shaft 3 for scanning the product wafer 2 along the irradiation range of the ion beam 1 while rotating.
A wafer wheel 5 including a plurality of wafer holders 4 each holding a product wafer 2 after being radially extended from the rotation shaft 3 is provided. This ion implanter has a carbon coating that is grounded and that passes through the irradiation range of the ion beam 1.
Metal rod-shaped member 7 which has been subjected to Ru der those disposed on the wafer wheel 5. These rod-shaped members 7 are arranged between the wafer holders 4, fixed to the rotating shaft 3, and grounded. At least one rod-shaped member 7 is attached to the rotating shaft 3. ing.

That is, even when such a configuration is adopted, when ion implantation is performed on the product wafer 2 as in the first embodiment, on the same locus as the product wafer 2 to be charged up at the time of ion implantation. Since the conductive rod-shaped member 7 is rotating at a high speed and these rod-shaped members 7 pass through the irradiation range of the ion beam 1 like the product wafer 2, the product wafer 2 is charged up. The electric charges of the spatial electromagnetic field generated by the above are absorbed by the rod-shaped member 7. Therefore, product wafer 2
The charge-up at the time of ion implantation is suppressed due to the absorption of charges by the rod-shaped member 7, and the charge-up of the product wafer 2 does not increase so much that it exceeds the withstand voltage of the insulating film.

(Third Embodiment) Furthermore, as illustrated in FIG. 3, a linear member 8 hung between the outer end position and the inner end position of each wafer holder 4, for example, carbon coated. the linear member 8 made of metal wire provided Ete bar member 7 second generation, it may be a ion implanter. Then, even at this time, the product wafer 2 that is charged up at the time of ion implantation
The linear member 8 having conductivity passes through the irradiation range of the ion beam 1 while rotating at a high speed on the same locus, so that the electric charge of the spatial electromagnetic field generated by the charge up of the product wafer 2 is linear member 8. Will be absorbed by
It is impossible that the charge-up of the product wafer 2 is so high that it exceeds the withstand voltage of the insulating film.

According to the second and third embodiments described above,
Since the product wafers 2 can be held by all the wafer holders 4, the production efficiency is superior to that of the first embodiment.

In each of the above-mentioned ion implanters,
As a conductor for forming the plate member 6 (Embodiment 1), the rod member 7 (Embodiment 2) and the linear member 8 (Embodiment 3), a conductor having higher electric conductivity is preferable, and at least a wafer holder. It is preferable that the electric conductivity is higher than that of aluminum, which is a general material of the wafer 4 and the wafer wheel 5. Furthermore, considering contamination, a material that does not volatilize at least at the ion implantation temperature is preferable. From these viewpoints, copper is preferable, and the one whose surface is coated with carbon or the like is more preferable. Further, since it is considered that the spatial electromagnetic field is formed above the surface of the product wafer 2, that is, on the ion irradiation source side, the plate-shaped member 6, the rod-shaped member 7, and the linear member 8 have their respective ion irradiation-side surfaces. It is more preferable that the height of the product wafer 2 is adjusted so as to project above the surface of the product wafer 2 on the ion irradiation side or be flush with the surface.

The ion implantation apparatus of the present invention described above is
OS type semiconductor device, especially MOS with extension structure
It is effective for manufacturing type semiconductors. That is, as shown in FIG. 4, in order to manufacture a MOS semiconductor device having an extension structure, first, a gate insulating film 11 and a gate electrode 12 are formed by stacking on the substrate 10, and then the gate electrode 12 is masked. And then perform shallow ion implantation to extend region 1
3 is formed. Then, sidewalls 14 are formed on both sides of the gate electrode 12, and then ion implantation is performed using the gate electrode 12 and the sidewall 14 as a mask to form a source region 15 and a drain region 16. To form the source region 15 and the drain region 16, the substrate 10
Ions must be implanted to a deep position of the gate electrode, and in the related art, a large amount of positive charges are accumulated in the gate electrode, and in some cases, the gate insulating film 11 may cause dielectric breakdown. However, by using each of the above-described ion implantation devices according to the present invention, the amount of positive charges accumulated is greatly reduced, and higher concentration ion implantation is performed without causing dielectric breakdown in the gate insulating film 11. Will be able to. Further, similarly, also in the ion implantation at the time of forming the gate electrode 12, high-concentration ion implantation can be performed without causing the dielectric breakdown of the gate insulating film 11.

[0036]

As described above, according to the ion implantation apparatus of the present invention, the conductive plate-like member and the rod which follow the same trajectory as the product wafer to be charged up at the time of ion implantation.
Jo member or linear member are rotated at a high speed, and is this
Since a conductive plate-shaped member, rod-shaped member, or linear member has passed through the ion beam irradiation range in the same way as the product wafer, the charge of the spatial electromagnetic field generated due to the charge-up of the product wafer becomes conductive. Plate-shaped member, rod-shaped member or linear
Since it will be absorbed by the member and the charge-up at the time of ion implantation in the product wafer will not increase to exceed the withstand voltage of the insulating film, it is possible to easily suppress the charge-up at the time of ion implantation. can get. Then, it is not necessary to remove the metal film for shielding after forming it on the insulating film, and the insulating film is damaged due to the removal of the metal film or the metal contamination of the product wafer or the bonding portion The advantage is that there is no occurrence of Further, according to the method for manufacturing a semiconductor device of the present invention, by using the above-described ion implantation device, the source region and the drain region of a MOS semiconductor having an extension structure are formed,
At the time of ion implantation into the gate electrode, it is possible to perform higher concentration ion implantation without causing dielectric breakdown of the gate insulating film.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a simplified internal structure of a wafer processing chamber provided in an ion implantation apparatus according to a first embodiment.

FIG. 2 is an explanatory view showing a simplified internal structure of a wafer processing chamber included in the ion implantation apparatus according to the second embodiment.

FIG. 3 is an explanatory view showing a simplified internal structure of a wafer processing chamber provided in the ion implantation apparatus according to the third embodiment.

FIG. 4 is a schematic diagram for explaining a method of manufacturing an extension structure MOS transistor.

FIG. 5 is an explanatory view showing a simplified internal structure of a wafer processing chamber provided in an ion implantation apparatus according to a conventional form.

[Explanation of symbols]

1 Ion Beam 2 Product Wafer 3 Rotating Shaft 4 Wafer Holder 5 Wafer Wheel 6 Conductive Plate Member 7 Conductive Rod Member 8 Conductive Wire Member

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-335585 (JP, A) JP-A-5-326435 (JP, A) JP-A-63-207126 (JP, A) 88031 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01J 37/317 C23C 14/48 H01J 37/20 H01L 21/265 603

Claims (3)

(57) [Claims] 1. An ion implantation apparatus having a wafer processing chamber for performing ion implantation on each of product wafers while integrally rotating a plurality of product wafers at a high speed along a trajectory passing through an irradiation range of an ion beam. The wafer wheel, which has a plurality of wafer holders that extend radially from the rotation axis and holds each of the product wafers, is grounded, passes through the ion beam irradiation range , and is mounted on the wafer holder. Then hold or
An ion implantation apparatus, characterized in that a materialized conductive plate member is provided. 2. A locus passing through an irradiation range of an ion beam
Therefore, do not rotate multiple product wafers integrally at high speed.
A wafer that performs ion implantation on each of the product wafers.
(C) An ion implanter equipped with a processing chamber, which extends each of the product wafers radially extending from the rotation axis.
Wafer wheel with multiple wafer holders to hold
Ground, and pass through the ion beam irradiation range.
And a conductive rod-shaped part placed between the wafer holders
An ion implanter, wherein a material or a linear member is provided . 3. Ion implantation according to claim 1 or 2.
Source and drain of MOS type semiconductor device using the device
Performing ion implantation to form the region and / or
Is characterized by including the step of implanting ions into the gate electrode.
Manufacturing method of semiconductor device .