JPS5978559A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS5978559A
JPS5978559A JP57188720A JP18872082A JPS5978559A JP S5978559 A JPS5978559 A JP S5978559A JP 57188720 A JP57188720 A JP 57188720A JP 18872082 A JP18872082 A JP 18872082A JP S5978559 A JPS5978559 A JP S5978559A
Authority
JP
Japan
Prior art keywords
emitter
transistor
width
circuit
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57188720A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0425712B2 (enrdf_load_stackoverflow
Inventor
Sadaji Tamura
田村　貞二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57188720A priority Critical patent/JPS5978559A/ja
Publication of JPS5978559A publication Critical patent/JPS5978559A/ja
Publication of JPH0425712B2 publication Critical patent/JPH0425712B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors

Landscapes

  • Logic Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
JP57188720A 1982-10-27 1982-10-27 半導体集積回路 Granted JPS5978559A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57188720A JPS5978559A (ja) 1982-10-27 1982-10-27 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57188720A JPS5978559A (ja) 1982-10-27 1982-10-27 半導体集積回路

Publications (2)

Publication Number Publication Date
JPS5978559A true JPS5978559A (ja) 1984-05-07
JPH0425712B2 JPH0425712B2 (enrdf_load_stackoverflow) 1992-05-01

Family

ID=16228597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57188720A Granted JPS5978559A (ja) 1982-10-27 1982-10-27 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS5978559A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6110267A (ja) * 1984-06-26 1986-01-17 Nec Corp モノリシック集積回路の製造方法
JPS6220363A (ja) * 1985-07-18 1987-01-28 Nec Corp 半導体集積回路
JPH04138720A (ja) * 1990-09-28 1992-05-13 Toshiba Corp 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6110267A (ja) * 1984-06-26 1986-01-17 Nec Corp モノリシック集積回路の製造方法
JPS6220363A (ja) * 1985-07-18 1987-01-28 Nec Corp 半導体集積回路
JPH04138720A (ja) * 1990-09-28 1992-05-13 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
JPH0425712B2 (enrdf_load_stackoverflow) 1992-05-01

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