JPS5973843U - Timing signal generation circuit - Google Patents
Timing signal generation circuitInfo
- Publication number
- JPS5973843U JPS5973843U JP17031882U JP17031882U JPS5973843U JP S5973843 U JPS5973843 U JP S5973843U JP 17031882 U JP17031882 U JP 17031882U JP 17031882 U JP17031882 U JP 17031882U JP S5973843 U JPS5973843 U JP S5973843U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- resistor
- signal
- generation circuit
- signal generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示すものであり、第1図は回
路図、゛第2図は各信号のタイミングチャートである。
1.2・・・入力端子、3・・・出力端子、Ql、 Q
2゜Q3・・・トランジスタ、C1・・・コンデンサ、
Dl・・・ダイオード、R1,R2,R3,R4,R5
・・・抵抗。The drawings show one embodiment of the present invention, and FIG. 1 is a circuit diagram, and FIG. 2 is a timing chart of each signal. 1.2...Input terminal, 3...Output terminal, Ql, Q
2゜Q3...transistor, C1...capacitor,
Dl...Diode, R1, R2, R3, R4, R5
···resistance.
Claims (1)
の信号をエミッタに印加するPNP型トランジスタQ1
と、前記信号を抵抗R2を介してベースに印加するNP
N型トランジスタQ2と、さらに第2入力端子2を介し
て一定のタイミングを有する信号をコンデンサC1及び
抵抗R3“で微分し、かつダイオードD1を介して抵抗
R4の両端に得られる正のパルスのみをベースに印加す
るトランジスタQlを有し、このトランジスタのエミッ
タを接地し、前記トランジスタQ1のコレクタに2前記
ダイオードD1のカソード側を、またこのベースヲ前記
トランジスタQ3のコレクタ及び前記トランジスタQ2
のエミッタに夫々接続すると共に、前記トランジスタQ
2のコレクタを抵抗R5を介して電源に接続し、このコ
レクタを出力端子3に接続してなり、前記第1入力端子
1からの信号を前記トランジスタQ1の電源として使用
している事を特徴とするタイミング信号発生回路。A PNP transistor Q1 applies a signal with undefined timing to the emitter from the first input terminal 1 via the resistor R1.
and an NP that applies the signal to the base via the resistor R2.
The N-type transistor Q2 and the second input terminal 2 are used to differentiate a signal having a constant timing with the capacitor C1 and the resistor R3, and only the positive pulses obtained across the resistor R4 are transmitted through the diode D1. The emitter of this transistor is grounded, the cathode side of the diode D1 is connected to the collector of the transistor Q1, and the base is connected to the collector of the transistor Q3 and the transistor Q2.
and the emitters of the transistors Q
2 is connected to a power supply via a resistor R5, and this collector is connected to an output terminal 3, and the signal from the first input terminal 1 is used as a power supply for the transistor Q1. timing signal generation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17031882U JPS5973843U (en) | 1982-11-09 | 1982-11-09 | Timing signal generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17031882U JPS5973843U (en) | 1982-11-09 | 1982-11-09 | Timing signal generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5973843U true JPS5973843U (en) | 1984-05-19 |
JPH0113463Y2 JPH0113463Y2 (en) | 1989-04-20 |
Family
ID=30371850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17031882U Granted JPS5973843U (en) | 1982-11-09 | 1982-11-09 | Timing signal generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5973843U (en) |
-
1982
- 1982-11-09 JP JP17031882U patent/JPS5973843U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0113463Y2 (en) | 1989-04-20 |
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