JPS5984910U - Muting signal generation circuit - Google Patents
Muting signal generation circuitInfo
- Publication number
- JPS5984910U JPS5984910U JP17894482U JP17894482U JPS5984910U JP S5984910 U JPS5984910 U JP S5984910U JP 17894482 U JP17894482 U JP 17894482U JP 17894482 U JP17894482 U JP 17894482U JP S5984910 U JPS5984910 U JP S5984910U
- Authority
- JP
- Japan
- Prior art keywords
- connection point
- resistors
- npn
- transistor
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す回路図、第２図及び第
３図は第１図の回路の動作を説明するための説明図であ
る。
Ａ・・・・・・安定化電源回路、Ｂ・・・・・・信号発
生部、Ｑ□・・・・・・ＮＰＮトランジスタ、Ｑ２・・
・・・・ＰＮＰ ）ランジスタ、Ｒ１−Ｒ５・・・・・
・抵抗、Ｃ１，Ｃ２・・・・・・コンデンサ。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams for explaining the operation of the circuit shown in FIG. 1. A: Stabilized power supply circuit, B: Signal generator, Q□: NPN transistor, Q2:
...PNP) transistor, R1-R5...
・Resistance, C1, C2...Capacitor.
Claims (1)
乃至第３の３つの抵抗をコレクタ側から順番に直列に挿
入し、第１及び第２の抵抗の接続点とアース間に第１の
コンデンサ、第２及び第３の抵抗の接続点とアース間に
ツェナーダイオード、そして前記ＮＰＮ ）ランジスタ
のベース及び第３の抵抗の接続点とアース間に第２のコ
ンデンサをそれぞれ接続し、前記ＮＰＮトランジスタの
コレクタ側を入力とし、エミッタ側を出力とする安定化
！源回路の前記ＮＰＮ ）ランジスタのベースと第３の
抵抗の接続点に第４の抵抗を介してベースが、前記安定
化電源回路の第２及び第３の抵抗の接続点にエミッタが
、そして第５の抵抗を介してアースにコレクタがそれぞ
れ接続されたＰＮＰ）ランジスタを備え、前記安定化電
源回路への直流電圧の供給を電源スィッチのオン・オフ
ｉこより切換える・毎に、前記ＰＮＰトランジスタのコ
レクタよりミューティング信号を発生するようになした
ミューティング信号発生回路。′The first between the collector bases of the NPN t-transistor
Three resistors are inserted in series from the collector side, the first capacitor is connected between the connection point of the first and second resistors and the ground, and the first capacitor is connected between the connection point of the second and third resistors and the ground. A Zener diode is connected to the base of the NPN transistor, and a second capacitor is connected between the connection point of the base of the NPN transistor and the third resistor, respectively, and the ground, and the collector side of the NPN transistor is used as an input, and the emitter side is used as an output for stabilization. ! The base is connected to the connection point between the base of the NPN (NPN) transistor and the third resistor of the power supply circuit via a fourth resistor, the emitter is connected to the connection point of the second and third resistors of the stabilized power supply circuit, and the emitter is connected to the connection point of the second and third resistors of the stabilized power supply circuit. Each time the supply of DC voltage to the stabilized power supply circuit is switched on or off by a power switch, the collector of the PNP transistor is connected to the ground through a resistor of A muting signal generation circuit that generates more muting signals. ′
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17894482U JPS5984910U (en) | 1982-11-29 | 1982-11-29 | Muting signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17894482U JPS5984910U (en) | 1982-11-29 | 1982-11-29 | Muting signal generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5984910U true JPS5984910U (en) | 1984-06-08 |
Family
ID=30388369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17894482U Pending JPS5984910U (en) | 1982-11-29 | 1982-11-29 | Muting signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984910U (en) |
-
1982
- 1982-11-29 JP JP17894482U patent/JPS5984910U/en active Pending
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