JPS5972552A - デ−タ転送方式 - Google Patents

デ−タ転送方式

Info

Publication number
JPS5972552A
JPS5972552A JP18424682A JP18424682A JPS5972552A JP S5972552 A JPS5972552 A JP S5972552A JP 18424682 A JP18424682 A JP 18424682A JP 18424682 A JP18424682 A JP 18424682A JP S5972552 A JPS5972552 A JP S5972552A
Authority
JP
Japan
Prior art keywords
memory
signal
cpu
control
cpu5
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18424682A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6127785B2 (cs
Inventor
Yoshiyuki Sakai
義行 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP18424682A priority Critical patent/JPS5972552A/ja
Publication of JPS5972552A publication Critical patent/JPS5972552A/ja
Publication of JPS6127785B2 publication Critical patent/JPS6127785B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP18424682A 1982-10-20 1982-10-20 デ−タ転送方式 Granted JPS5972552A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18424682A JPS5972552A (ja) 1982-10-20 1982-10-20 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18424682A JPS5972552A (ja) 1982-10-20 1982-10-20 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS5972552A true JPS5972552A (ja) 1984-04-24
JPS6127785B2 JPS6127785B2 (cs) 1986-06-27

Family

ID=16149938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18424682A Granted JPS5972552A (ja) 1982-10-20 1982-10-20 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS5972552A (cs)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54939A (en) * 1977-06-06 1979-01-06 Panafacom Ltd Bus priority use control system
JPS5416334U (cs) * 1977-07-06 1979-02-02

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54939A (en) * 1977-06-06 1979-01-06 Panafacom Ltd Bus priority use control system
JPS5416334U (cs) * 1977-07-06 1979-02-02

Also Published As

Publication number Publication date
JPS6127785B2 (cs) 1986-06-27

Similar Documents

Publication Publication Date Title
KR890002330B1 (ko) 멀티프로세서 시스템
JPH06139097A (ja) インサーキットエミュレータ
JPH0258649B2 (cs)
EP1209565A3 (en) Multicore dsp device having shared program memory with conditional write protection
JPS58501560A (ja) マイクロプロセツサ
JPH0543151B2 (cs)
JPS5972552A (ja) デ−タ転送方式
US4180855A (en) Direct memory access expander unit for use with a microprocessor
US5828859A (en) Method and apparatus for setting the status mode of a central processing unit
JPS5927938B2 (ja) 多重処理装置
JPH051504B2 (cs)
JPS6331935B2 (cs)
JPS59133629A (ja) Ｄｍａ転送制御方式
JPS59188779A (ja) ベクトル処理装置
JPS6391756A (ja) 記憶装置の部分書き込み命令処理方式
JPS59146361A (ja) デユアルポ−トメモリ制御回路
JPS599744A (ja) 高速ｄｍａ転送起動回路
JPH05334234A (ja) 高速ｄｍａ転送装置
JPS62173560A (ja) メモリアクセス制御回路
JPS61241851A (ja) 読出し回路
JPS59123063A (ja) マルチ・プロセツサ・システムの共有資源アクセス方式
JPH02204852A (ja) バス制御回路
JPH04248609A (ja) 情報処理装置、情報処理装置に接続される付属装置、及び、情報処理装置と付属装置とを含む情報処理システム
JPS59139453A (ja) 命令実行制御方式
JPH02118837A (ja) 割込み制御装置