JPS597221B2 - Multilayer wiring manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor integrated circuit device (hereinafter referred to as IC) with electronic components.
This invention relates to a method for manufacturing multilayer wiring, which is frequently used in the production of (abbreviated as ).

As the degree of integration of ICs increases, the interconnections between devices become more complex and require more crossovers.

Therefore, multilayer wiring becomes necessary. When manufacturing multilayer wiring on this IC chip, conductive films and insulating films that serve as interconnections are alternately laminated, and an interlayer insulating film is used to connect lower and upper wirings. A through hole is provided in the. However, as shown in FIG. 1 is a plan view of the multilayer wiring on a conventional IC chip, and FIG.
Although the wiring area 1a, 2a at the through-hole portion requires 15 to 20 ttm, this lowers the wiring density and makes layout difficult.

In the figure, 3 is a field silicon oxide film on the surface of a silicon wafer 4 on which elements are formed, and 5 is a silicate glass film that is an interlayer insulating film.
Reference numeral 4a denotes a diffusion layer serving as an active region of the element, which is of a conductivity type opposite to that of the silicon wafer 1, and forms a PN junction therewith. Further, in FIG. 1, the area indicated by the dotted line is a through hole provided in the silicate glass film 5. This is because when manufacturing a multilayer wiring, the size of the through hole is set to be larger than the lower wiring so that the field silicon oxide film 3 under the lower wiring 1 is not etched when selectively etching the silicate glass film 5. In addition, the size of the upper layer wiring 2 is determined by passing the lower layer wiring 1 through a through hole during selective etching when forming the upper layer wiring 2 into a wiring pattern.
This is because the hole needs to be made larger than the through hole so as not to be etched.

Therefore, the present invention solves the above-mentioned conventional drawbacks and improves the wiring density by reducing the wiring width at the through-hole part in multilayer wiring as much as possible. An object of the present invention is to provide a method for manufacturing multilayer wiring that facilitates layout.

In order to achieve the object of the present invention, in the present invention, a lower wiring film is formed on the surface of the first insulating film, and is etched with an etching solution different from the etching solution JO for etching the first insulating film. or forming a second insulating film made of a material having an etching rate higher than that of the first insulating film over the entire surface of the lower wiring film; forming a through hole 15 in the first layer of material, which is etched with an etching solution different from the etching solution for etching the lower layer wiring, or having an etching rate higher than the etching rate of the lower layer wiring; forming a conductive film to cover the lower wiring film and the second insulating film whose top 20 surfaces are exposed by the through hole;
forming a second conductor film of the same material as the lower wiring film to cover the first conductor film; and selectively removing the second conductor film to form a second conductor film. forming a wiring pattern 25 of the second conductive film, and utilizing the difference in the material of the first conductive film with respect to the lower wiring film and the second conductive film. The method further comprises a step of selectively removing the first conductive film exposed from the second conductive film to form a wiring pattern (530) of the second conductive film that is self-aligned. , will be specifically explained using examples according to the present invention.

FIGS. 2 to 5 are a plan view and a cross-sectional view taken in the direction of the arrows, showing the method for manufacturing multilayer wiring in an IC according to an embodiment of the present invention in the order of steps.

The present invention will be explained in detail in the order of steps using the same figure.

(g) Form 40 contact holes in the field silicon oxide film 12 on the surface of the silicon wafer 11 on which device formation has been completed (FIG. 2).

In addition, in the same figure, 11a is the silicon wafer 11
This is a diffusion layer of a conductivity type opposite to that of the wafer 11, and is an element active region forming a PN junction with the wafer 11. Next, aluminum is vacuum-deposited, and then a wiring pattern is formed by photo-etching to obtain the lower wiring film 13.

As a selective etching solution for the aluminum vapor deposited film 13, a phosphoric acid type (phosphoric acid + nitric acid + glacial acetic acid) or an alkaline type (caustic potassium + potassium ferricyanide) can be used. Next, a base film 1 for an interlayer insulating film is applied to the surfaces of the lower wiring film 13 and the field silicon oxide film 12.
form 4.

As this base film 14, a fiigold silicon oxide film 1 is used.
A polyimide resin film or the like is used that can be selectively etched with an etching solution that does not attack the second layer. Since hydrazine hydrogen chloride is used as the selective etching solution for the polyimide resin film 14, the field silicon oxide film 12 is not attacked by this solution. This polyimide resin film 14
In order to make the interlayer insulation more complete, a silicate glass film such as a silicon oxide film or a phosphosilicate glass PSG film is formed by CVD as necessary, or a spin-on glass SOG film is applied on the base film 14. A silicate glass film 14a or the like may be provided. The interlayer insulating film such as the silicate glass film 14a can be etched using an etching solution for selectively etching it (the etching solution for the silicate glass film 14a is a buffer solution prepared by diluting hydrofluoric acid with water and ammonium fluoride). A material that does not corrode the base film 14 (for example, a polyimide resin film) is used. Next, through holes are formed in the interlayer insulating films 14 and 14a.

If there is a silicate glass film 14a, it is photoetched and an opening window is formed in the through hole portion (
Figure 2). This opening window is made of a polyimide resin film 14 that is not eroded by the photoetching solution (buffer solution);
Since it is located under the opening window, it can be made as small as possible. b) Selective etching of the self-aligned polyimide resin film 14 using hydrazine hydrogen hydroxide through the opening window in the through-hole portion of the silicate glass film 14a (third step).
figure).

When manufacturing the through holes in the interlayer insulating films 14 and 14a, the selective etching solution (hydrazine hydrade) for the polyimide resin film 14, which is the underlying film, does not attack the field silicon oxide film 12, so as shown in FIG. As shown in FIG. 2, the entire surface of the through-hole portion of the lower wiring film 13 can be exposed. Therefore, the smallest possible through hole can be obtained. In addition, since ohmic contact can be made with the upper wiring film over the entire width of the lower wiring film 13, the wiring resistance at the through-hole portion can be reduced, and moreover, the formation of through-holes in highly reliable multilayer wiring can be achieved by self-aligning. can be easily obtained (layout is also easier). The lower wiring film (as the base film for the upper wiring film)
A conductive film made of materials such as silicon, molybdenum, tungsten, etc., which is selectively etched with an etching solution that does not attack the aluminum evaporated film 13 (
In this embodiment, a silicon film 15) is formed.

The silicon film 15 can be formed by vapor deposition or the like, and a mixed solution of hydrofluoric acid, phosphoric acid, and nitric acid (HF) is used as an etching solution.
-HNO3 based etching solution) etc. are used. Next, in order to reduce the wiring resistance on the surface of this silicon film 15, an aluminum vapor deposition film 15a or the like (selectively etched using a photoetching solution that does not attack the base film 15) is formed as necessary. This is then photo-etched to form a wiring pattern as soil layer wiring (fourth step).
figure).

(d) Using the aluminum evaporated film 15a as the soil layer wiring as a mask, unnecessary portions of the silicon film 15 as the base film are etched off by self-alignment to obtain the upper layer wiring (FIG. 5).

Although not shown, a surface protective film is then formed on these.

As mentioned above, in addition to using interconnect films or insulating films with different etching solutions, it is also possible to use interconnect films or insulating films with different etching speeds, and the present invention can be applied to various methods of manufacturing multilayer interconnects. .

As described above, the method for manufacturing multilayer wiring according to the present invention makes it possible to make the through holes as small as possible, and also to obtain perfect ohmic contact with low wiring resistance in these parts.

Since the interlayer insulating film and wiring film in the through-hole area can be formed by self-alignment, combined with the above-mentioned factors, it is possible to easily obtain multilayer wiring with extremely high wiring density, and the layout is also easy, allowing for fine processing. Easy and highly reliable multilayer wiring can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view and a sectional view taken in the direction of arrows showing a conventional multilayer wiring, and FIGS. 2 to 5 are I
FIG. 3 is a plan view and a cross-sectional view taken in the direction of arrows illustrating the manufacturing method of the multilayer wiring in step C in order of steps. 1, 13...Lower wiring film, 2, 15, 15a.
... Upper wiring film, 3, 12 ... Field silicon oxide film, 4, 11 ... Silicon wafer, 4a, 11a ... Diffusion layer, 5, 14 ,1
4a...Interlayer insulating film.

Claims (1)

[Claims] 1. A lower wiring film is formed on the surface of the first insulating film, and is etched with an etchant different from the etchant for etching the first insulating film, or etched at a rate higher than the etching rate of the first insulating film. forming a second insulating film made of a material having high speed over the entire surface of the lower wiring film;
forming a through hole in the second insulating film by taking advantage of the difference in materials, and etching with an etching solution different from the etching solution for etching the lower layer wiring, or etching the lower layer wiring. forming a first conductive film made of a material having a higher etching rate than the etching rate, covering the lower wiring film and the second insulating film whose surfaces are exposed by the through hole;
forming a second conductor film made of the same material as the lower wiring film to cover the conductor film, and selectively removing the second conductor film to form a wiring pattern of the second conductor film. and the difference in the material of the first conductor film with respect to the lower wiring film and the second conductor film, the wiring pattern exposed from the wiring pattern of the second conductor film is 1st
1. A method for manufacturing a multilayer wiring comprising the step of selectively removing a conductive film to form a wiring pattern that is self-aligned with the wiring pattern of the second conductive film.