JPS5972038U - dial circuit - Google Patents

dial circuit

Info

Publication number
JPS5972038U
JPS5972038U JP16687682U JP16687682U JPS5972038U JP S5972038 U JPS5972038 U JP S5972038U JP 16687682 U JP16687682 U JP 16687682U JP 16687682 U JP16687682 U JP 16687682U JP S5972038 U JPS5972038 U JP S5972038U
Authority
JP
Japan
Prior art keywords
signal
series resistor
circuit
delay
dial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16687682U
Other languages
Japanese (ja)
Inventor
橋本 義照
Original Assignee
八重洲無線株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 八重洲無線株式会社 filed Critical 八重洲無線株式会社
Priority to JP16687682U priority Critical patent/JPS5972038U/en
Publication of JPS5972038U publication Critical patent/JPS5972038U/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来回路例、第2図は本考案の回路例、第3図
はタイミングチャート、第4図は第2図回路におけるC
KとU/D信号の関係を示す。
Fig. 1 is an example of a conventional circuit, Fig. 2 is an example of a circuit according to the present invention, Fig. 3 is a timing chart, and Fig. 4 is a C in the circuit of Fig. 2.
The relationship between K and the U/D signal is shown.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] タイアルエンコーダの発生する2つの位相の異るパルス
信号より、CKパルスと、ダイアルの回転方向または周
波数のU/Dを示すU/D信号を検出してCPUに入力
する回路において、UID信号出力とCPU入力の中間
に直列抵抗と直列抵抗の出力側の並列コンデンサより成
る信号遅延回路を設け、かつ該信号遅延回路の直列抵抗
と並列にダイオードを接続することによりU/D信号の
前縁の遅延を小さく、後縁の遅延を大きく設定したこと
を特徴とするダイアル回路。
UID signal output in a circuit that detects a CK pulse and a U/D signal indicating the dial rotation direction or frequency U/D from two pulse signals with different phases generated by the tile encoder and inputs them to the CPU. By providing a signal delay circuit consisting of a series resistor and a parallel capacitor on the output side of the series resistor between the input and the CPU input, and connecting a diode in parallel with the series resistor of the signal delay circuit, the leading edge of the U/D signal is A dial circuit characterized by having a small delay and a large trailing edge delay.
JP16687682U 1982-11-02 1982-11-02 dial circuit Pending JPS5972038U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16687682U JPS5972038U (en) 1982-11-02 1982-11-02 dial circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16687682U JPS5972038U (en) 1982-11-02 1982-11-02 dial circuit

Publications (1)

Publication Number Publication Date
JPS5972038U true JPS5972038U (en) 1984-05-16

Family

ID=30365236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16687682U Pending JPS5972038U (en) 1982-11-02 1982-11-02 dial circuit

Country Status (1)

Country Link
JP (1) JPS5972038U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134565A (en) * 1974-04-10 1975-10-24
JPS5278350A (en) * 1975-12-25 1977-07-01 Fujitsu Ltd Phase synchronous oscillator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50134565A (en) * 1974-04-10 1975-10-24
JPS5278350A (en) * 1975-12-25 1977-07-01 Fujitsu Ltd Phase synchronous oscillator

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