JPS596568A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS596568A JPS596568A JP11594482A JP11594482A JPS596568A JP S596568 A JPS596568 A JP S596568A JP 11594482 A JP11594482 A JP 11594482A JP 11594482 A JP11594482 A JP 11594482A JP S596568 A JPS596568 A JP S596568A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- lead wire
- hybrid integrated
- conductor layer
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Abstract
Description
【発明の詳細な説明】
本発明は絶縁基板上に形成された導電体に電子部品をろ
う付けして構成する混成集積回路の製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a hybrid integrated circuit constructed by brazing electronic components to a conductor formed on an insulating substrate.
第１図〜第４図はこの種の混成集積回路が従来方法によ
って製造される様子を示す図であって、ここでは電子部
品として電力半導体素子（１）が予めろう付けされたヒ
ートシンク（２）を絶縁基板（３）に形成された導電体
層（４）へろう付けする場合を示している。すなわち、
従来方法においてはまず、第１図に示すように電力半導
体素子（１）とヒートシンク（２）とがろう付けされる
。次に、第２図に示すように絶縁基板（３）の表面に形
成された導電体層（４）に予備半田が施された後、前記
ヒートン／り（２）が導電体層（４）の上に仮置きされ
たうえでリフローされ、導電体層（４）に半田付けされ
る。この後、第３図に示すような外部配線用リード線（
５）が導電体層（４）の外部配線接続部へ半田（６）に
よって接続される。これによって、第４図に示すような
断面形状の混成集積回路が形成される。1 to 4 are diagrams showing how this type of hybrid integrated circuit is manufactured by a conventional method. Here, a heat sink (2) to which a power semiconductor element (1) as an electronic component is pre-brazed is shown. A case is shown in which the conductor layer (4) is brazed to the conductor layer (4) formed on the insulating substrate (3). That is,
In the conventional method, first, as shown in FIG. 1, a power semiconductor element (1) and a heat sink (2) are brazed together. Next, as shown in FIG. 2, after preliminary soldering is applied to the conductor layer (4) formed on the surface of the insulating substrate (3), the heaton/resist (2) is applied to the conductor layer (4). After being temporarily placed on top, it is reflowed and soldered to the conductor layer (4). After this, connect the lead wire for external wiring (as shown in Figure 3).
5) is connected to the external wiring connection part of the conductor layer (4) by solder (6). As a result, a hybrid integrated circuit having a cross-sectional shape as shown in FIG. 4 is formed.
とζろが、上述し未従来方法ではヒートシンク（２）と
外部配線用リード線の接続が別々の工程で行なわれてい
るため、外部配線用リード線を半田付けする際にヒート
シンク（２）と導電体層（４）との接合部分の半田も溶
けてヒートシンク（２）の位置がずれてしまうことがあ
り、半田付は作業に一定の熟練が要求されるなど作業性
が悪く、製造時間が長びくという欠点があると同時に、
自動化がしにくいとめう欠点があった。However, in the unconventional method mentioned above, the heat sink (2) and the external wiring lead wire are connected in separate steps, so when the external wiring lead wire is soldered, the heat sink (2) and the external wiring lead wire are connected in separate steps. The solder at the joint with the conductor layer (4) may also melt and the position of the heat sink (2) may shift, and soldering requires a certain degree of skill, making it difficult to work and reducing manufacturing time. It has the disadvantage of being long-lasting, but at the same time,
The drawback was that it was difficult to automate.
本発明はこのような欠点を解決するためになされたもの
で、その目的は作業性が良く、かつ自動化が容易となる
混成集積回路の製造方法を提供することにある。The present invention has been made to solve these drawbacks, and its purpose is to provide a method for manufacturing a hybrid integrated circuit that is easy to work with and easy to automate.
このために本発明は、電子部品に予め外部配線用リード
線を仮固定した後、この電子部品を外部配線用リード線
とともに導電体に一括してろう付けするようにしたもの
である。For this purpose, in the present invention, after an external wiring lead wire is temporarily fixed to an electronic component in advance, the electronic component is collectively brazed to a conductor together with the external wiring lead wire.
以下、図示する実施例に基づいて本発明を説明する。Hereinafter, the present invention will be explained based on illustrated embodiments.
第５図および第６図は本発明によって混成集積回路が形
成される様子を示す図であって、まず電力半導体素子（
１）とヒートシンク（２）とがろう付けされた後、第５
図に示すように外部配線用リード線（５ａ）がヒートシ
ンク（２）の側面に溶接などの手段によって仮固定され
る。次に、導電体層（４）に予備半田が施された後、ヒ
ートシンク゛（２）が導電体層（４）の上に置かれたう
えでリフローされ、外部配線用リード線（５ａ）と共に
導電体層（４）へ一括して半田付けされる。これによっ
て、第６図に示すような断面形状の混成集積回路が形成
される。FIG. 5 and FIG. 6 are diagrams showing how a hybrid integrated circuit is formed according to the present invention.
1) and the heat sink (2) are brazed, the fifth
As shown in the figure, an external wiring lead wire (5a) is temporarily fixed to the side surface of the heat sink (2) by means such as welding. Next, after preliminary soldering is applied to the conductor layer (4), the heat sink (2) is placed on the conductor layer (4) and reflowed, together with the external wiring lead wire (5a). It is soldered all at once to the conductor layer (4). As a result, a hybrid integrated circuit having a cross-sectional shape as shown in FIG. 6 is formed.
このように本発明によれば、電子部品に外部配線用リー
ド線を仮固定した後、この電子部品を絶縁基板上の導電
体に一括してろう付けするようにしたため、ろう付は作
業を簡略化できると共に作業性が向上し、自動化もし易
くなるなど製造上において良好な効果が得られる。As described above, according to the present invention, after the lead wire for external wiring is temporarily fixed to the electronic component, the electronic component is brazed all at once to the conductor on the insulating substrate, which simplifies the brazing work. Good effects can be obtained in manufacturing, such as improved work efficiency and ease of automation.
第１図〜第４図は従来方法によって混入集積回路が製造
される様子を示す図、第５図、第６図は本発明の方法に
よって混成集積回路が製造される様子を示す図である。
（１）・・・・電−カ・半導体素子、（２）・・・・ヒ
ートシンク、（３）・・・・絶縁基板、（４）・・・・
導電体層、（６）・・・・半田、（５） ＃ （５ａ）
・・・・外部配線用リード線。
代 理 人 葛 野 信 −1 to 4 are diagrams showing how a hybrid integrated circuit is manufactured by the conventional method, and FIGS. 5 and 6 are diagrams showing how a hybrid integrated circuit is manufactured by the method of the present invention. (1)...Electric power/semiconductor element, (2)...Heat sink, (3)...Insulating substrate, (4)...
Conductive layer, (6)...Solder, (5) # (5a)
...Lead wire for external wiring. Agent Shin Kuzuno −
Claims (1)
て構成する混成集積回路の製造方法において、前記電子
部品に予め外部配線用リード線を仮固定した後前記電子
部品を前記導電体に外部配線用リード線とともに一括し
てろう付けすることを特徴とする混成集積回路の製造方
法。In a method for manufacturing a hybrid integrated circuit in which an electronic component is brazed to a conductor formed on an insulating substrate, an external wiring lead wire is temporarily fixed to the electronic component in advance, and then the electronic component is attached to the conductor. A method for manufacturing a hybrid integrated circuit characterized by brazing together with lead wires for external wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11594482A JPS596568A (en) | 1982-07-02 | 1982-07-02 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11594482A JPS596568A (en) | 1982-07-02 | 1982-07-02 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596568A true JPS596568A (en) | 1984-01-13 |
Family
ID=14675031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11594482A Pending JPS596568A (en) | 1982-07-02 | 1982-07-02 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596568A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56100430A (en) * | 1980-01-11 | 1981-08-12 | Toshiba Corp | Fixing method for power transistor to substrate |
-
1982
- 1982-07-02 JP JP11594482A patent/JPS596568A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56100430A (en) * | 1980-01-11 | 1981-08-12 | Toshiba Corp | Fixing method for power transistor to substrate |
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