JPS5927537A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5927537A JPS5927537A JP57138183A JP13818382A JPS5927537A JP S5927537 A JPS5927537 A JP S5927537A JP 57138183 A JP57138183 A JP 57138183A JP 13818382 A JP13818382 A JP 13818382A JP S5927537 A JPS5927537 A JP S5927537A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- metal plate
- electrode
- insulating substrate
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
−この発明は、電力半導体モジュールなどに使用する半
導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION - The present invention relates to improvements in semiconductor devices used in power semiconductor modules and the like.
近年電子機器の発達は著しく、その小形軽量化が急速に
進んでいる。これらの基をなすものは、半導体装置の小
形化及び信頼性の向上によるものである。このなかでも
、特に、）ランジスタの大電流容量化に伴う中容量の電
力用半導体装置としての応用が活発になっておシ、小形
軽量化を図ったパワーモジールの分野への適用も多く々
ってきている。BACKGROUND ART In recent years, electronic devices have made remarkable progress, and their size and weight are rapidly decreasing. These advances are based on the miniaturization and improved reliability of semiconductor devices. Among these, in particular, transistors have been increasingly applied as medium-capacity power semiconductor devices as transistors have become larger in current capacity, and are also increasingly being applied to the field of power modules that are smaller and lighter. ing.
従来のこの種の半導体装置を第１図に平面図で示す。図
はパワーモジュールにＩ重用するトランジスタの場合を
示し、（１）は放熱金属板で、上面にアルミナ材などか
らなる絶縁基板（２）が固着されている。この絶縁基板
上にはコレクタ電極（３）、ペース電極（４）及びエミ
ッタ電極（５）が固着式れである０コレクタ電極（３）
上にはトランジスタ素子（６）が固着されている０、ま
た、コレクタ電極（３）から外部電極（３ａ）が、ペー
ス電極（４〕から外部電極（４ａ）が、エミッタ電極（
５）から外部電極（５ａ）が、それぞれ上方に曲げ起こ
されて引出づれている。トランジスタ素子（６）上面の
ペースポンディングパッド及びエミッタポンディングパ
ッドと、対応するペース電極（４）、エミッタ電極（５
）をそれぞれアルミ線（７）でボンディング接続してい
る。A conventional semiconductor device of this type is shown in a plan view in FIG. The figure shows the case of a transistor that is used heavily in a power module. (1) is a heat dissipation metal plate, and an insulating substrate (2) made of alumina material or the like is fixed to the upper surface. On this insulating substrate, a collector electrode (3), a pace electrode (4), and an emitter electrode (5) are fixedly attached.
The transistor element (6) is fixed on the top of 0, and the collector electrode (3) to the external electrode (3a), the pace electrode (4) to the external electrode (4a), and the emitter electrode (
5), the external electrodes (5a) are bent upward and drawn out. The pace bonding pad and emitter bonding pad on the upper surface of the transistor element (6) and the corresponding pace electrode (4) and emitter electrode (5)
) are connected by bonding with aluminum wires (7).
上記従来の装置の組立ては、次のようにしていた。まず
、絶縁基板（２）の両面に所要はんだ付は箇所にメタラ
イズ層を施す。放熱金属板（１）上にはんだ薄片を介し
絶縁基板（２）を置く。つづいて、この絶縁基板上にそ
れぞれはんだ薄片を介しコレクタ電極（３）、ベース電
極（４）、エミッタ電極（５）を載せる０さらに、コレ
クタ電極（３） ｉにはんだ薄片を介しトランジスタ素
子（６）を配置する０このように・各部品が載せられた
放熱板（１）を組立設備の熱板（図示していない）−上
に載せ、加熱して各部品をはんだ融着する。、つぎに、
トランジスタ素子（６）上面のポンディングパッドと対
応する各電極とを、それぞれアルミ線（７）により、ワ
イヤボンドする。各電極の先端側を上方に曲げ起こし各
種の外部電極（３ａ） 。The above conventional device was assembled as follows. First, a metallized layer is applied to both sides of the insulating substrate (2) at the required soldering locations. An insulating substrate (2) is placed on the heat dissipation metal plate (1) with a thin solder piece interposed therebetween. Subsequently, a collector electrode (3), a base electrode (4), and an emitter electrode (5) are placed on this insulating substrate through solder thin pieces, respectively.Furthermore, a transistor element (6) is placed on the collector electrode (3) i through a solder thin piece. ) Place the heat sink (1) on which each component is placed on a hot plate (not shown) of the assembly equipment, and heat to solder and fuse each component. ,next,
The bonding pads on the upper surface of the transistor element (6) and the corresponding electrodes are wire-bonded using aluminum wires (7). Various external electrodes (3a) by bending the tip side of each electrode upward.
（４ａ） 、 （６ａ’）を形成する。これらの各外部
電極の各上端側を残し、外装容器（図示は略す）に入れ
樹脂封止し製品が完成される。(4a) and (6a') are formed. Leaving the upper end sides of each of these external electrodes intact, they are placed in an outer container (not shown) and sealed with resin to complete the product.
上記従来の半導体装置は、数点の部品を一度に同時には
んだ溶着しなければならず、はんだが溶融すると各部品
を水平方向に往復してこすり付けねばならず、ずれ易く
て位置決めが非常に困難であり、また、はんだの融着が
不完全な箇所が生じるなどの作業」二の欠点があシ、ｌ
ｉ＞性−ヒからも信頼性からも問題があった。In the conventional semiconductor device described above, several parts must be soldered together at the same time, and once the solder melts, each part must be rubbed back and forth in the horizontal direction, making it easy to shift and positioning it very difficult. In addition, there are two drawbacks: 1. There are places where the solder is incompletely fused.
There were problems both in terms of quality and reliability.
この発明は、絶縁基板の上面に各電極を、下面に放熱金
属板を高温ろう付は固着し、所定の電極上に半導体素子
をはんだ接合し、各部品の装着作業を容易にし、特性及
び信頼性を向上した半導体装置を提供することを目的と
している○以下、この発す］の一実施例による半導体装
置を、パワーモジュールに使用するトランジスタの場合
を図について説明する。第２図は放熱金属板と各電極を
固着した絶縁基板部の斜視図でるる。アルミナ材などか
らなる絶縁基板（１２）には、下面に銅板などからなる
放熱金属板（１１）を、上面にコレクタ電極−，ペース
電極（１４）及びエミッタＴ（を極０５１を、それぞれ
銀ろう又は高温はんだなどによる高温ろう付けで固着し
ている。In this invention, each electrode is fixed to the upper surface of an insulating substrate and a heat dissipating metal plate is fixed to the lower surface by high temperature brazing, and a semiconductor element is soldered onto a predetermined electrode, thereby facilitating the installation work of each component and improving characteristics and reliability. A semiconductor device according to an embodiment of the present invention, which aims to provide a semiconductor device with improved performance, will be described with reference to the drawings in the case of a transistor used in a power module. FIG. 2 is a perspective view of the insulating substrate portion to which the heat dissipating metal plate and each electrode are fixed. An insulating substrate (12) made of alumina material etc. has a heat dissipating metal plate (11) made of a copper plate etc. on the bottom surface, a collector electrode, a pace electrode (14) and an emitter T (pole 051) on the top surface, respectively with silver solder. Or it is fixed by high-temperature brazing with high-temperature solder.
第３図及び第４図は、第２図の状態から半導体菓子をワ
イヤボンドした半導体装置の平面図及び側面図である。3 and 4 are a plan view and a side view of a semiconductor device in which a semiconductor confectionery is wire-bonded from the state shown in FIG. 2.
コレクタ電極Ｈ上にはトランジスタ素子（６）が固着さ
れ、対応する各電極と傾アルミ線（７）でワイヤボンデ
ィング接続している。コレクタ電極（Ｉ萄、ペース電極
（ｌ→及びエミッタ電極（１５）の先端側が第２図で示
す鎖線の位置から上方に曲げ起こされ、外部電極（１３
ａ） 、 （１４ａ）及び（１５ａ）が形成されている
。A transistor element (6) is fixed on the collector electrode H, and connected to each corresponding electrode by wire bonding with an inclined aluminum wire (7). The tips of the collector electrode (I), the pace electrode (I→), and the emitter electrode (15) are bent upward from the position indicated by the chain line in FIG.
a) , (14a) and (15a) are formed.
上記一実施例の装置の組立ては、次のようにする。絶縁
基板０２）の上面及び下面に“、所要ろう付は箇所にメ
タライズ層を施す０このメタライズ層が施場れた絶縁基
板θ２）の上面に各電極（１３ａ） 、 （１４ａ）及
びＤ５ａ）を、下ｍ】に放熱金属板（１１）を高温ろう
付けによシ固着する。コレクタ電極Ｏａｔ上にはんだ薄
片を介しトランジスタ素子（６）を配置する。上記のよ
うに上部に各部品が配設された放熱金属板（１１）を組
立設備の熱板上に載せて加熱し、トランジスタ素子（６
）をはんだ融着によシ接合する。つぎに、トランジスタ
素子（６）と対応する各電極Ｈ、ｔ＋ｓｌをそれぞれア
ルミ線（７）によシワイヤボンドする０つづいて、各電
極ｔｈ３ｔ 、 Ｈ及び０５）の先端側を上方に曲げ起
こし、外部電極（１３ａ） 、 （１４ａ）及び（１５
ａ ）を形成する。この組立体を外装容器（図示は略す
）に入れ、引出きれている外部電極の上端部を残し、樹
脂封止し製品が完成する。The apparatus of the above embodiment is assembled as follows. On the upper and lower surfaces of the insulating substrate 02), a metallized layer is applied to the required brazing points.On the upper surface of the insulating substrate θ2) on which this metallized layer is applied, each electrode (13a), (14a) and D5a) is applied. , the heat dissipation metal plate (11) is fixed to the bottom m] by high-temperature brazing.The transistor element (6) is placed on the collector electrode Oat via a thin solder piece.Each component is arranged on the upper part as described above. The heat dissipating metal plate (11) is placed on a hot plate of assembly equipment and heated, and the transistor element (6
) are joined by solder fusion. Next, each electrode H, t+sl corresponding to the transistor element (6) is wire-bonded to the aluminum wire (7). Next, the tip side of each electrode th3t, H and 05) is bent upward and the external electrode (13a), (14a) and (15
a) form. This assembly is placed in an outer container (not shown) and sealed with resin, leaving the upper end of the external electrode completely pulled out, to complete the product.
なお、上記実施例セは半導体装置の半導体素子としてト
ランジスタ素子（６）の場合を説明したが、他の積の半
導体菓子の場合にも適用できるものである。In the above embodiment, the transistor element (6) is used as the semiconductor element of the semiconductor device, but the present invention can also be applied to semiconductor confectionery of other products.
以上のように、この発明によれば、絶縁基板に放熱金属
板と各電極とを高温ろう付は固着し、半導体素子のみを
所定の電極上にはんだ接合したので、各部品の位置決め
が容易で結合作業が簡単になり、はんだ融着不良が減少
し、特性及び信頼性が向上式れる。As described above, according to the present invention, the heat dissipating metal plate and each electrode are fixed to the insulating substrate by high-temperature brazing, and only the semiconductor element is soldered onto the predetermined electrode, making it easy to position each component. It simplifies the bonding process, reduces solder fusion defects, and improves characteristics and reliability.
第１図は従来の半導体装置を示す外装前の平面図、第２
回ないし第４図はこの発明の一実施例による半導体装置
を示し、第２図は絶縁基板に放熱金属板及び各電極を固
着した状態の斜視図、第３図は外装前の平面図、第４図
は第３図の装置の側面図である。
６・・・トランジスタ素子、７・・・アルミ線、１１・
・・放熱金属板、工２・・・絶縁基板、１３・・・コレ
クク電極、１４・・ペース電極、１５・・エミッタ電極
、１３ａ 、 １４ａ 。
１５ａ・・・外部電極
なお、図中同一符号は同−又は相当部分を示す。
代理人 葛野信−（外１名）Figure 1 is a plan view of a conventional semiconductor device before packaging;
4 to 4 show a semiconductor device according to an embodiment of the present invention, FIG. 2 is a perspective view of a heat dissipating metal plate and each electrode fixed to an insulating substrate, FIG. 3 is a plan view before exterior packaging, and FIG. FIG. 4 is a side view of the apparatus of FIG. 3. 6...Transistor element, 7...Aluminum wire, 11.
... Heat radiation metal plate, work 2 ... Insulating substrate, 13 ... Collector electrode, 14 ... Pace electrode, 15 ... Emitter electrode, 13a, 14a. 15a...External electrode Note that the same reference numerals in the drawings indicate the same or corresponding parts. Agent Shin Kuzuno (1 other person)
Claims (1)
電極が固着式れ、これらの電極のうち所定の電極上に半
導体素子がはんだ付は接合され、上記半導体素子と対応
する上記電極とがワイヤボンドされた半導体装置におい
て、上記絶縁基板は上面及び下面のろう付は烙れる部分
に、めらかしめメタライズ層を施してあり、下面に上記
放熱金属板を、上面に上記各種の電極をそれぞれ高温ろ
う付けによ多接合して固着したことを特徴とする半導体
装置。A heat dissipating metal plate is fixed to the lower surface of the insulating substrate, various electrodes are fixed to the upper surface, and a semiconductor element is soldered onto a predetermined electrode among these electrodes, and the semiconductor element and the corresponding electrode are connected to each other. In the wire-bonded semiconductor device, the insulating substrate is coated with a smooth metallized layer on the upper and lower surfaces where brazing is hot, the heat dissipating metal plate is on the lower surface, and the various electrodes are on the upper surface. A semiconductor device characterized in that each of the semiconductor devices is bonded and fixed together by high-temperature brazing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57138183A JPS5927537A (en) | 1982-08-07 | 1982-08-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57138183A JPS5927537A (en) | 1982-08-07 | 1982-08-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5927537A true JPS5927537A (en) | 1984-02-14 |
Family
ID=15215993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57138183A Pending JPS5927537A (en) | 1982-08-07 | 1982-08-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5927537A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561086A (en) * | 1993-06-18 | 1996-10-01 | Lsi Logic Corporation | Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches |
| US5653891A (en) * | 1992-06-03 | 1997-08-05 | Seiko Epson Corporation | Method of producing a semiconductor device with a heat sink |
| JP2006215149A (en) * | 2005-02-02 | 2006-08-17 | Funai Electric Co Ltd | Projector |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5641174A (en) * | 1979-08-29 | 1981-04-17 | Daicel Ltd | Feed hopper |
-
1982
- 1982-08-07 JP JP57138183A patent/JPS5927537A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5641174A (en) * | 1979-08-29 | 1981-04-17 | Daicel Ltd | Feed hopper |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5653891A (en) * | 1992-06-03 | 1997-08-05 | Seiko Epson Corporation | Method of producing a semiconductor device with a heat sink |
| US5561086A (en) * | 1993-06-18 | 1996-10-01 | Lsi Logic Corporation | Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches |
| JP2006215149A (en) * | 2005-02-02 | 2006-08-17 | Funai Electric Co Ltd | Projector |
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