JPS5963738U - data transfer device - Google Patents
data transfer deviceInfo
- Publication number
- JPS5963738U JPS5963738U JP15795782U JP15795782U JPS5963738U JP S5963738 U JPS5963738 U JP S5963738U JP 15795782 U JP15795782 U JP 15795782U JP 15795782 U JP15795782 U JP 15795782U JP S5963738 U JPS5963738 U JP S5963738U
- Authority
- JP
- Japan
- Prior art keywords
- data
- transfer device
- output
- serial
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dc Digital Transmission (AREA)
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ転送装置のブロック図、第２図（
１本考案の実施例のブロック図である。図において、
１・・・・・・入力アダプタ、２・・・・・・シリアル
パラレル変換器、３・・・・・・データレジスタ、４．
１２・・・３ステート、バッファ、５・・・・・・コン
トロール部、６・・・・・・ステータスレジスタ、７・
・・・・・データバ支、１１・・・・・・オーバーラン
防止用レジスタ、である。Figure 1 is a block diagram of a conventional data transfer device, and Figure 2 (
1 is a block diagram of an embodiment of the present invention; FIG. In the figure, 1... input adapter, 2... serial parallel converter, 3... data register, 4.
12...3 state, buffer, 5...control section, 6...status register, 7...
. . . Data bar support, 11 . . . Overrun prevention register.
Claims (1)
ルパラレル変換器と、このシリアルパラレル変換器の出
力を読込む第１のデータレジスタと、この第１のデータ
レジスタにデータがセットされるとこの第１のデータレ
ジスタの出力を読込む第２のデータレジスタと、前記第
１のデータレジスタが所定時間内）こデータを出力しな
いとき前記第２および第１の各データレジスタの出力を
交互に出力するよう制御する制御部とを含むデータ転送
装置。A serial-parallel converter that converts input serial data of a predetermined length into parallel data, a first data register that reads the output of the serial-parallel converter, and a first data register that reads the output of the serial-parallel converter. a second data register that reads the output of the first data register; and when the first data register does not output this data within a predetermined time period, outputs the outputs of the second and first data registers alternately. A data transfer device including a control unit that controls the data transfer device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15795782U JPS5963738U (en) | 1982-10-19 | 1982-10-19 | data transfer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15795782U JPS5963738U (en) | 1982-10-19 | 1982-10-19 | data transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5963738U true JPS5963738U (en) | 1984-04-26 |
Family
ID=30348101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15795782U Pending JPS5963738U (en) | 1982-10-19 | 1982-10-19 | data transfer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5963738U (en) |
-
1982
- 1982-10-19 JP JP15795782U patent/JPS5963738U/en active Pending
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