JPS5960718A - セルフクロック装置 - Google Patents

セルフクロック装置

Info

Publication number
JPS5960718A
JPS5960718A JP16952382A JP16952382A JPS5960718A JP S5960718 A JPS5960718 A JP S5960718A JP 16952382 A JP16952382 A JP 16952382A JP 16952382 A JP16952382 A JP 16952382A JP S5960718 A JPS5960718 A JP S5960718A
Authority
JP
Japan
Prior art keywords
signal
output
counter
circuit
input data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16952382A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0452553B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Michio Kawase
道夫 川瀬
Tadahiro Wada
和田　忠博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16952382A priority Critical patent/JPS5960718A/ja
Publication of JPS5960718A publication Critical patent/JPS5960718A/ja
Publication of JPH0452553B2 publication Critical patent/JPH0452553B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
JP16952382A 1982-09-30 1982-09-30 セルフクロック装置 Granted JPS5960718A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16952382A JPS5960718A (ja) 1982-09-30 1982-09-30 セルフクロック装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16952382A JPS5960718A (ja) 1982-09-30 1982-09-30 セルフクロック装置

Publications (2)

Publication Number Publication Date
JPS5960718A true JPS5960718A (ja) 1984-04-06
JPH0452553B2 JPH0452553B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-08-24

Family

ID=15888078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16952382A Granted JPS5960718A (ja) 1982-09-30 1982-09-30 セルフクロック装置

Country Status (1)

Country Link
JP (1) JPS5960718A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579042A1 (fr) * 1985-03-18 1986-09-19 Bull Micral Procede d'extraction d'un signal d'horloge synchrone a partir d'un signal code en simple ou double intensite, et dispositif permettant la mise en oeuvre du procede

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579042A1 (fr) * 1985-03-18 1986-09-19 Bull Micral Procede d'extraction d'un signal d'horloge synchrone a partir d'un signal code en simple ou double intensite, et dispositif permettant la mise en oeuvre du procede
US4809304A (en) * 1985-03-18 1989-02-28 Bull, S. A. Method of extracting a synchronous clock signal from a single- or double-density coded signal, and apparatus for performing the method

Also Published As

Publication number Publication date
JPH0452553B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-08-24

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