JPS5958485A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument that controls the tempo of automatic performance.

Conventionally, music data such as pitch and note length are stored, and this music data is read out according to a predetermined tempo to automatically generate musical tones and display key positions on V and LA boards. There are known electronic musical instruments that control the generation of the tempo clock that automatically advances the performance in relation to the speed and slowness of the keyboard performance, or stop the generation of the tempo clock. lII+
There is also known an electronic musical instrument in which the frequency is fully controlled to match the progress of the mf performance and the automatic performance.

However, although the former type of conventional electronic musical instruments is very effective for key-pressing practice, it automatically proceeds according to a predetermined tempo regardless of the difficult-to-play parts. When faced with a conflict, many people give up on practicing. In addition, in the latter case, if a difficult part of the performance is hit during the performance and the pressing of the needle is delayed, the progress of the automatic performance will be paused until the key is pressed; Since the automatic performance proceeds according to the previous tempo, the progress of the automatic performance becomes discontinuous, and there is a problem that the performance by the keys pressed at that point and the automatic performance are out of sync.

This invention was made in view of the above-mentioned circumstances.
It is an object of the present invention to provide a 113: child instrument suitable for key pressing practice by slowing down the progress of automatic performance in front of a note that is played exactly like V in a small instrument room.

Accordingly, the present invention provides an electronic musical instrument having an automatic performance device, which stores data regarding the pitch to be played on the keyboard, reads out the above ↑ and 1 data in accordance with the automatic performance tempo of the automatic performance device; The performance difficulty level of the ¥1-note to be played is detected based on the stored data, and the automatic performance tempo of the automatic performance device is changed according to the detected performance difficulty level, so that the performance is performed before a difficult-to-play note. I'm trying to slow down the progress of automatic play.

This invention will be explained in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument to which the present invention is applied. As shown in FIG. 1, the keyboard 1 has a key switch on each external power supply that is linked to key operations, and depending on the pressed key, the key switch corresponding to that key is turned on. The pressed key detection circuit 2 scans the key switch, detects a key switch that is turned on, that is, a pressed key, and outputs key information (key code) KC representing the key in a time-division manner, and also detects whether the key is pressed. A binary level key-on signal KON indicating this is output.

The key code KC is, for example, a 2-bit octave code B2. Bl
and a 4-bit note code representing the names of 12 notes within one octave, N4. N3. N,,N.

This is a 6-pit binary coded signal consisting of

The key code KG and key-on signal KON outputted from the key press detection circuit 2 are applied to the sound generation channel assignment circuit 3 and the melody pitch data extraction circuit 4.

The sound generation channel allocation circuit 3 receives, as other inputs, obbligado pitch data ON outputted from a chord/obligado data extraction circuit 200, which will be described later, and a plurality of key codes indicating chord constituent tones outputted from the subordinate tone forming circuit 5. CK C1 and a key code BKC indicating the bass tone output from the bass tone forming circuit 6 are added.

The subordinate note forming circuit 5 forms a plurality of key codes CKC indicating chord constituent notes based on the chord name data CH output from the chord/obligado data extraction circuit 200. Note that the chord name data CH is a 6-bit binary code consisting of 4-bit data indicating the name of the root note of the chord (see Table 1) and 2-bit data indicating the type of chord (major, mica, seventh). .

To show an example of key code CKC formation in the subordinate note forming circuit 5, when the chord type is major, perfect 1 is used for the root note.
Forms a key code CKC that indicates notes that have an interval relationship of degree, major third, and perfect fifth, and when the chord type is mica, the interval relationship of perfect 1st, minor 3rd, and perfect 5th with respect to the root note. When the chord type is seventh, a key code CKC is formed that indicates a note that has an interval relationship of a perfect 1rpL, a major third, and a minor seventh with respect to the root note.

The bass tone forming circuit 6 generates a bass tone based on the chord name data CI outputted from the chord/obligado data extraction circuit 200 (and the bass pattern signal 13P outputted from the automatic accompaniment pattern signal generation circuit 7). A key code B K C'fIC is generated.The automatic accompaniment pattern signal generating circuit 7 will now be explained.

The automatic accompaniment pattern signal generation circuit 7 generates an 11th sound generation timing signal CT, a bass sound generation timing signal BT, a rhythm pattern signal RP, and a bass pattern signal corresponding to the rhythm selected by a rhythm selection switch (not shown). Tempo control circuit 400 whose BP will be described later
It is generated by the tempo clock TCL output from the tempo clock TCL, and is composed of a pattern memory and an address counter.

The pattern memory stores a plurality of 111-tone sound generation timing patterns, bass sound generation timing patterns, rhythm patterns, and bass patterns for each rhythm. The patterns for each rhythm stored in this pattern memory are selected by the rhythm selection switch, and each of the selected patterns is read out 11 times using the count value of the address counter counting the tempo clock TCI4 as an address signal. Note that the '80 tone generation timing signal CT and the bass tone generation timing signal BT are signals indicating the generation timing of the automatic chord tone and the automatic bass tone, respectively hD, and the rhythm pattern signal RP is the f! of the rhythm tone to be generated. l! The base pattern signal BP is a signal indicating the pitch relationship corresponding to the root tone of the automatic bass note to be produced.

The bass tone forming circuit 6 adds the key code indicating the root tone of the chord among the input chord name data CH to the base pattern signal BP, thereby indicating a bass tone having a predetermined interval relationship with respect to the root tone. Create key code BKC'i. Note that the bass sound forming circuit 6 receives the bass pattern signal B.
If P corresponds to the interval of a major third and the chord type of the Fang U note name data CH is mica, the pace pattern signal B
Pif: Modify and add to correspond to the interval of a minor third.

The sound generation channel allocation circuit 3 is a channel f to which the key code KC output from the key press detection circuit 2 is exclusively allocated.
A channel to which the Oprigard pitch data ON outputted from the i-note/oprigard data extraction circuit 200 is exclusively assigned, a channel to which the key code CKC indicating the chord constituent tones outputted from the subordinate tone forming circuit 5 is exclusively assigned, and a bass tone. It has a sufficient number of sound generation channels consisting of channels exclusively assigned to the key code B K Ci indicating the bass sound output from the formation circuit 6, and each of the above key codes is appropriately assigned to these sound generation channels, and the key codes are assigned to each channel. The stored key code KC* is outputted to the tone forming circuit 8 in a time-divisional manner.

The musical tone forming circuit 8 forms a musical tone signal based on the key code KC applied from the sound generation channel allocation circuit 3 in a time-division manner. Note that the key code KC output from the key press detection circuit 2
The musical tone signal formed based on is subjected to opening/closing envelope control by the key-on signal KOH output from the key press detection circuit 2, and is also controlled by the key code CKC indicating chord constituent notes.
The musical tone signals formed based on the key codes BK and C indicating the bass notes are respectively generated by the bass sound generation timing signal C generated from the automatic accompaniment pattern signal generation circuit 7.
Opening/closing envelope control is performed based on T and bass sound generation timing signal BT.

Musical tone signal amplifier 9 formed by the musical back formation circuit 8
It is amplified by the speaker 10, where it is sounded as a melody, chord, bass note, and obbligato -r+.

In addition, rhythm sound signals indicating various rhythm sounds are generated according to the rhythm pattern signal RP generated from the rhythm sound source circuit 11Fi and the automatic accompaniment pattern signal generation circuit 7, and are added to the speaker 10 via the amplifier 9, Pronounce it as a sound.

Next, tempo control for automatic performance of an electronic musical instrument will be explained.

First, the data format of the automatic performance data output from the external recording means 12 will be explained.

The external recording means 12 is a magnetic card/chive, a punch card, a bar code, etc., and as shown in FIG. Data is recorded in the form of serial data according to the order of description. Note that mark data DM, -DMS for identifying each data is recorded at the head of each data.

The melody pitch data and the oprigade pitch data each indicate pitch, and are composed of 6-bit binary codes (see Table 1).

The melody note length data and obbligado note length data each indicate the length of a note or a rest, that is, the note length, and are composed of 6-pinto binary codes. An example of the data is shown in Table 2.

The second table chord data includes O II pitch name data indicating the chord name of the chord to be generated and timing data indicating the chord generation timing, and is composed of 6-pit and 10-bit binary codes, respectively.

Note that the chord name data is read out along with the reading of the obligado pitch data, and the timing data is read out after the opligado pitch data of the opligado notes to be sounded at the same time is transferred to the data memory 14, which will be described later. This corresponds to the storage address in the data memory 14.

Each of the above data recorded in the external recording means 12 is read by the music data input device 13 in the form of serial data. The music data input device ff￥, ]3 converts the read serial data into parallel data, and saves the melody pitch data, melody note length data, obbligado pitch data, obbligado note length data, and chord data as a data memo. 4, and write control data including mark data DM to DM5 is also supplied to an iRAM (random, access, memory) write control circuit 15.

Data Memo January 4 has a storage area for each data group, and writing to and reading from the corresponding storage area of each data group is performed using five counters that output address signals corresponding to each storage area. This is done by the address counter 16 consisting of 16a to 16e.

RAM■Including sub-control circuit 15 This circuit controls writing of each data group supplied from the music data input device 13 to the data memory 14 for each storage area corresponding to each data in the data memory 14. First, the music data input device 13 When the mark data I) M is inputted, the counter 1.6a of the address counter 16 corresponding to the storage area of the melody pitch data becomes operational, and the melody pitch data is sent from the music data input device 13. The counter 16a is incremented each time. The counter 16a outputs the counted value as an address signal to the data memory 14, and writes melody pitch data ti+ into the address indicated by the address signal.

Note that the RAM write control circuit 15 writes mark data DMt.
At the same time as f is input, the counter 16a is initially set so that the address signal of the counter 16a indicates the start address of the storage area for melody pitch data.

When writing of all the melody pitch data is completed in this way, the RAM write control circuit 15 outputs the mark data DM2.
is input, and the melody note length data is written in the storage area corresponding to the melody note length data in the data memory 14 from the top address of the storage area in the same manner as described above. Below, R.A.
The M write control circuit 15 writes mark data DM3 and DM4.
, DM5'ff: Every λ, opligado pitch data, opligado note length data, and chord data are written into the storage area corresponding to the mark data from the top address of the storage area.

Next, a case will be described in which the start switch 17f is turned on after all automatic performance data have been written into the data memory J4.

When the start switch 17 is turned on, the RAM read control circuit 18 initializes the address counter 16 so that each color 7p of the address counter 16 indicates the start address of the corresponding storage area, and then reads the data memo data. 4, the address counter 16 sequentially reads out melody pitch data and melody note length data corresponding to the first and second notes of the melody, and obbligado pitch data and obbligado note length data corresponding to the first note of the opligado. control.

That is, the RAM read control circuit J8 is a counter 16a of the address counter 16 corresponding to the storage area of melody pitch data and melody note length data.

The melody pitch data and melody note length data corresponding to the first note of the melody are read out from the data memory 14 based on the address signals of the respective counters 16a and I6b, and the melody note length data and the melody note length data corresponding to the first note of the melody are read out from the data memory 14 based on the address signals of the respective counters 16a and I6b.
bt count up and read out melody pitch data and melody note length data corresponding to the second note of the melody. Similarly, by enabling the counters 16c and 16d of the address counter J6 corresponding to the storage areas of the obligard pitch data and the opligado note length data, and incrementing the respective counters 16c and 16d, the first note of the opligado is activated. Read the oprigard height data and obligard note length data corresponding to .

Note that the RAM read control circuit 18 uses the address counter 1
Counters 16a and 16bf of 6: output the next melody read request signal MNR every time the counters 16a and 16bf of the address counter 16 count up, and turn on the next obligate read request signal every time the counters 16C and 16d of the address counter 16 count up.
Output R. In addition, the RAM read control circuit 18 controls the address counter 16 corresponding to the storage area of the chord data. Read all chord data.

The data output circuit 19 includes a one-tone search circuit 19at, and among each data read from the data memo 14,
Obligado pitch data ON1, obbligado note length data OLI, and O Melody note length data ML2f: output to the performance difficulty level detection circuit 300. Note that the chord search circuit 19a searches the data memory 14 based on the address signal output from the counter 16C of the address counter 16 when reading the oprigade pitch data.
The timing data of chord data indicating the same address as the address signal is searched from the chord data read out at high speed from the chord data, and a pair of chord name data CH1 with this timing data is outputted.

Melody data retrieval circuit] 00 receives melody pitch data MN2 and melody note length data ML2 from the data output circuit 19, a next melody read request signal MNR from the RAM read control circuit 18, and a tempo control circuit 400 to be described later. A tempo clock TCL is added, and the melody tones (1) to be played are based on these signals.
Melody pitch data MHI of melody sound with musical notes
and melody note length data MLl, melody pitch data MN and melody note length data ML of the melody sound being played, a stop command signal MP used for stopping the output of the tempo clock from the tempo control circuit 400,
and a read command signal MLU';i of melody data (melody pitch data and melody note length data) from the data memory 14.

FIG. 3 shows details Mnm of the melody data extraction circuit 100.
In this example, when the next melody read request signal MNR is applied as melody data is read from the RAM read control circuit 18, the latch circuits 101 and 10
2 are melody pitch data MN2 and melody note length data M added from the data output circuit 19, respectively.
T, 2f luffs, latch circuits 103 and 104 latch the melody pitch data MNI and melody note length data MLIt- which were previously latched by latch circuits 101 and 102, respectively, and melody note length color/reset 105 is reset. In addition, since the signal MNR is output once when the start switch 170 is turned on immediately after the start switch 170 is turned on, the melody pitch data MNI and the melody note latched by the latch circuits 101 and 102 are The long data MLI corresponds to the first note of the melody that is about to be played, and the latch circuits 103 and 104 contain silence pitch data (key codes other than the key codes shown in Table 1) and silence length data. (all “0”) are latched.

Melody pitch data M latched by the latch circuit 101
NI is a performance difficulty detection circuit 300 and a tempo control circuit 40.
0↓ and the melody note length data MLI and melody pitch data MN added to the display device 20 and latched by the latch circuits 102 and 103 are respectively added to the performance difficulty detection circuit 300 and latched by the latch circuit 104. The melody note length data ML is applied to the B input of the comparator 106, the performance difficulty detection circuit 300, and the tempo control circuit 400.

The display device 20 is comprised of lamps disposed on each side, and displays the key to be pressed by lighting the lamp corresponding to the input melody pitch data MNI. Therefore, the display device 20 lights up the key corresponding to the first note of the melody based on the melody f height data MNI.

The comparator 106 has the parallel output of the upper bits excluding the lower two bits from the melody note length counter 105 that counts the tempo clock TCL added to the A input as note length data, and each note length added to the input and B input. Compare the data, and when they match, the melody note length match signal M
Output LEQ.

In this case, the melody note length counter 105 is reset by the signal MNR and outputs all non-note length data (
After resetting, three tempo clocks TCL are applied to the melody note length counter 105, and the fourth tempo clock TCL is applied to the stop command signal MP (FIG. 4(d)), which will be described later.
(see FIG. 4(C)), the comparator 106 applies a match signal MLEQ (“1”) (see FIG. 4(C)) to the AND circuit 107, thereby enabling the AND circuit 107. .

After the Norody note length counter 105 is reset, three tempo clocks TCL are input (see FIG. 4(a)), and the outputs of the lower two bits are both "1", so the AND circuit 108 inputs the three tempo clocks TCL. Via Iko No. 1
Therefore, the AND circuit 107 outputs the fourth tempo clock TCL to the melody note length counter 105.
Stop command signal MP (
Referring to FIG. 4(d), the signal is outputted to the tempo control circuit 400 and also to the AND circuit 109.

Here, the melody performance corresponding to the first note of the melody is performed at the performance time t KON (see Figure 4 (1)).
, when the fourth tempo clock TCL is output from the tempo control circuit 400 after resetting the note length counter 105,
The AND circuit 109 receives the tempo clock TCLi melody data read command signal MLU (see FIG. 4(e)).
It is output to the RAM read control circuit 18 as

When the RAM read control circuit 18 receives the read command signal MLU, it immediately counts up counters 1.8a and 18b of the address counter 18 and reads out the melody data corresponding to the third note of the melody from the data memo January 4. At the same time, the next melody read request signal MNR (fourth
(see figure (f)).

As a result, the latch circuits 101 and 102 each have melody pitch data MN corresponding to the second note of the melody.
latch circuits 103 and 104 output melody pitch data MN and melody note length data ML corresponding to the first note of the melody, respectively.

The display device 20 lights up the key to be pressed next based on the melody pitch data MNl corresponding to the second note of the melody output from the latch circuit 101, and displays the key to be pressed next.
``i11i11 input circuit'' Inputs melody note length data ML corresponding to the first note of the melody output from 04.

The comparator 106 has a melody note length counter 105 at its A input.
Note length data corresponding to the time after KON is added from the melody performance time t to the time t when these note length data match. outputs the melody note length match signal MLEQ in the same manner as described above (see FIG. 5(C)). 10
5, when the third tempo clock TCL is output, the AND circuit 109 outputs the stop command signal MP (see FIG. 5(d)), and when the fourth tempo clock TCL is output, the AND circuit 109 outputs the read command signal MLIJ ( (See Figure 5(e)). In addition, as shown in FIG. 5(b), there is a point tK in performance 11.
If ON is earlier than the coincidence time 1°, the melody coincidence signal MKEQ does not stop the fourth and subsequent tempo clocks TCL after the coincidence time 1o.

In this way, the melody data retrieval circuit 100i1, the melody height data MNJ and the melody note length data ML1 of the melody sound of one note, each time the melody is played.
The melody pitch data MN and melody note length data ML of the melody sound being played, the stop command signal MP, and the melody read command signal MLU are taken out.

The chord/oprigard data retrieval circuit 200 receives obbligard pitch data ONl, oprigard note length data OL1, and chord name data CH] from the data output circuit 19, and receives the next obbligard readout request from the RAM readout control circuit 18. A signal ONR is applied, and a tempo clock TCL is applied from a tempo control circuit 400, which will be described later.
Based on these signals, the melody data extraction circuit 1
00, obbligado pitch data ON of the obbligado note to be automatically played, chord name data C1l corresponding to the chord/bass note to be automatically played, and obbligado data from the data memory 14 (oprigade pitch data and Opliguard code length data) read command signal ML
This is to take out U.

Figure 6 shows the chord/obligado data extraction circuit 200.
This shows a detailed configuration example of the RAM read control circuit 18.
When the next obbligard vesical suction signal ONR is applied as the obbligard data is read from the latch circuit 2, the latch circuit 2
01, 2 (12 and 2031-i, respectively) Obligado pitch data O added from the data output circuit 19
NJ, chord name data CH1, and obbligard note length data oL1f: latched, and mebrigade note length counter 204 is reset by this signal ONH.

Immediately after the start switch 170 is turned on, the signal ONR is not output, so the latch circuits 201 and 203 latch the obligate pitch data ONI and the oblicard note length data OLI corresponding to the first note of the e-nio pre-guard. Also, the latch circuit 202
In this case, the chord name data CH1 indicating the chord to be pronounced together with the first note of the obbligado is also not latched. The latch circuit 203 latches unsigned length data (all 0'').

Obligate code length data OL (unsign length data) latched by the latch circuit 203 is applied to the input of the comparator 2050B. To the A input of the comparator 205, the parallel output of the upper bits excluding the lower two pits of the oprigade code length counter 204 for counting the tempo clock TCL is added as code length data.

Comparator 205 compares each code length data applied to A input and B input, and outputs an obbligato match signal 0LEQ when they match. Obrigado note length counter 20
4 outputs unsigned data like the melody note length counter 105, so the comparator 205 (applies the match signal 0LEQ to the AND circuit 206, and the AND circuit 20 (
i';c Enable operation.

The obbrigade note length counter 204 inputs three tempo clocks TCL after being reset, and the outputs of the lower two pits are both 1", so the AND circuit 207 outputs a signal "1" via the AND circuit 206f: Output.

Here, a melody corresponding to the first note of the melody is played, and the tempo control circuit 400 and note length counter 20
When the fourth tempo clock TCT is output after the reset of 4, the AND circuit 208 outputs the read command signal OL of this tempo clock TCL if obligated data.
It is output as U to the RAM read control circuit 18.

When the RAM read control circuit I8 inputs the read command signal OLU, the counters 18c and 1 of the address counter 18
8dfc immediately counts up and Obligado's second
Data memo of obbligado data corresponding to the note January 4th
At the same time as reading from
Outputs NR.

The latch circuit 201 turns on the mepri-guard pitch data corresponding to the first note of the opuri-guard by the cono signal ON H.
I latch and output this as obbligado pitch data ON. Since this oprigade pitch data ON is applied to the aforementioned sound generation channel assignment circuit 3 (FIG. 1), the speaker 10 produces the first oprigade tone. The latch circuit 202 also stores chord name data C) indicating a chord to be sounded with the first note of obbligado.
I] and outputs it as chord name data CH to the subtone forming circuit 5 and bass tone forming circuit 6, and the latch circuit 203 latches obbligado note length data OL1 corresponding to the [th] note of the obbligado. This is then output to the comparator 2050B input as the note length data OL of the currently played obbligado note. Further, the obligatory code length counter 204 is reset by the signal ONR.

The comparator 205 has the mark length data OL added to the B input, and the A
The code length data corresponding to the time after reset is added from the obbligard code length counter 204 to the input, and when these pieces of code length data match, the opliguard code length match signal 0LEQ-i is outputted in the same manner as described above. Then, after the signal 0LEQ is output, the AND circuit 206 outputs the third tempo clock TCL from the tempo control circuit 400 to the obbligard note length counter 204.
08k operation is enabled, and when the fourth tempo clock TCL is output, the AND circuit 208 outputs this tempo clock TCL as a read command signal OLU.

In this way, the chord/obligado data extraction circuit 20
When a melody is played and the tempo clock TCL is output from the tempo control circuit 400, 0 takes out the obligate pitch data ON, the chord name data CII, and the opligado data read/output command signal OLU.

Performance JiIt, Difficulty Detection Frequency Detection Circuit tJ-1 Detects the performance difficulty of the note to be played, and outputs tempo change data corresponding to this performance difficulty to the tempo control circuit 400 to control the tempo. This is to change and control the tempo based on the performance of the notes in the circuit 400.

FIG. 7 shows a detailed configuration example of the second performance EI level detection circuit 300, which is composed of four detectors 301 to 304 and an adder 305 for detecting the performance EI level. . The detectors 301 to 304 each detect whether the note to be played falls into any performance difficulty level F as shown in the third column.
Data corresponding to the performance difficulty level depending on whether J≦ (“1
” to “4”) are output.

In Table 3, the pitch difference detector 301 has a subtracter and a read-only memory (ROM) that stores the performance difficulty classifications shown in Table 3 above and data corresponding to the classifications. - the absolute value of the pitch difference data between melody pitch data M N and MNI is equalized, and this absolute value and the
The data corresponding to the matching performance difficulty classification are inputted. As is clear from Table 3, when the change in pitch is large, the key press is too slow, so the larger the change in pitch, the more tempo change data S TM
The above data forming P'Th is set to a large value.

The white/black key detector 302 has a ROM that stores the key code corresponding to the white key, and when the manually input melody pitch data MNI matches the data stored in the ROM, it returns "2".
If there is a match 1 to no match, data corresponding to [4] is output.

That is, since black keys are more difficult to press than white keys, when the key to be played is a black key, the data forming the tempo change data STMP is set to a large value.

The fast progression detector 303 includes a ROM that stores performance difficulty classifications shown in Table 3 and data corresponding to the classifications, and input melody note length data M L , MLI, and ML.
The added note length data is compared with the performance difficulty classification, and if the performance matches, 1 is output as data corresponding to the difficulty classification. In other words, if the added note length is short, the performance before and after the note to be played will be faster, so in this case, the tempo change data STMP
Increase the above data to form.

The note length detector 304 has a ROM that stores the performance difficulty classifications shown in Table 3 and data corresponding to the classifications, and compares the input melody note length data ML with the performance difficulty classifications and determines whether they match. Data corresponding to the performance difficulty level is output. In other words, if the note length of the currently played note is short, it is difficult to press the next key, so the shorter the note length of the currently played note, the thicker the data forming the tempo change data STMP is. .

Data corresponding to the performance difficulty level outputted from each of the detectors 301 to 304 is added to an adder 305.

Adder 305 adds these data and outputs this added value to tempo control circuit 400 as tempo change data STMP corresponding to the performance difficulty level. The tempo change data STMP is data indicating a value of "5" to "16", and the higher the value is, the more difficult it is to perform.

The tempo control circuit 4()0 receives tempo change data STM.
In addition to P, melody γ↑high button M N ], melody length data ML and stop command 1d MP are added from the melody data retrieval circuit 100, and Media read request signal M
NR is added, and the melody bamboo height data extraction circuit 4
Melody pitch data MMN based on keys pressed on keyboard 1 from
is added, and controls to stop the tempo clock TCL based on these signals, and also controls the frequency of the tempo clock TCI. Note that the melody row height data extraction circuit 4 extracts only the key code C manually inputted at 9 o'clock when the key-on signal KON rises among the key codes KC input in a time-divisional manner from the press σ detection circuit 2. Extract as row height data MMN.

FIG. 8 shows an example of a detailed 1t-Y configuration of the tempo control circuit 400.

The selection switch 401 is used to determine the rise condition of the melody match signal MKEQ, and contacts 401a and 401b of the selection switch 401 are connected to OR circuits 40
3 and the output of comparator 404 are added.

Since the OR circuit 403 takes the OR condition of the melody pitch data MMN (6-bit binary code (see Table 1)), when any #l is pressed on the keyboard J (any key on), the pressed key is outputs a signal “1” at times. Note that the key range of the keyboard 1 does not include the key t that corresponds to the key code where all d6 bits are 'θ''.
The melody pitch data MNI of the note that precedes the note by one note and the melody pitch data MMN indicating the pressed key on keyboard 1 are added, and when these pitch data match, that is, the proper pitch is set for key m1. When a hammer is pressed, it outputs a signal "1"°.

Therefore, when the selection switch 401 Fi is connected to its movable contact piece 401C'fc contact 401a, a signal "'1" is output when any key is pressed on the keyboard 1, and when connected to the contact 40]b, the key is pressed. Signal ``1'' when there is a match
The signal N 1 ++ output from the selection switch 40 is applied to the AND circuit 408 via the OR circuit 407.The other input of the AND circuit 408 receives the next melody read request signal M N The output of the inverter 409 that inverts Ri is added, but the merotea and the bladder output request signal MNR are
is output immediately after the melody read command signal MLU as shown in FIGS. 4(f) and 5(f), so the AND circuit 408 is enabled to operate when a melody coincidence is detected. Therefore, the signal P1'' output from the selection switch 401 is applied to the D control flop 410 via the OR circuit 407 and the AND circuit 408.

The D clip-flop 4]0 delays the input signal ゛°1'' by a predetermined time and converts it into an all-melody matching signal MKEQ('
1”).This melody matching signal MK
Since the EQ is fed back to the D flip-flop 410 via the OR circuit 4()7 and the AND circuit 408, it is held until the next melody output request signal MNR is output (see FIGS. 4(b) and 4(b)). (See Figure 5).

Next is the tempo control episode! The operation of 34.00 will be explained. Before starting automatic performance, latch circuits 413 and 414
and 415 each latch frequency information (tempo data) of the reference tempo clock. Further, the counter 423 is preset so that the counted value matches the tempo data.

The tempo data latched by latch circuits 413 and 414 are applied to the A input and B input of arithmetic circuit 412, respectively. The arithmetic circuit 412 takes the average value of the two people's tempo data and outputs this average value as new tempo data. Note that the tempo data of this combination matches the tempo data of the reference tempo clock. The tempo data output from the arithmetic circuit 412 is applied to the latch circuits 413 and 4]5 via the limiter 416. Here, the limiter 416 limits the maximum and minimum values of the tempo data output from the arithmetic circuit 412.

As described above, the latch circuit 415 latches the tempo data of the reference tempo clock in advance and applies it to the comparator 417. A count value from a counter 418 that counts high-speed variable clock pulses φ output from a variable frequency divider 430, which will be described later, is added to the other input of the comparator 417 as tempo data. When they match, a signal "1" is output to the AND circuit 419.

AND circuit 4] 9 U variable clock pulse φ to other inputs
* is added, so the signal "1" is output from the comparator 4]7.
This clock pulse φ is output to the load input LD of the latch circuit 415, the reset terminal R1 of the counter 418, and the AND circuit 420 only when the clock pulse φ is applied.

As a result, the latch circuit old 5 latches the tempo data input from the limiter 416 and outputs it to the comparator 417, and the counter 418 is reset, counts the variable clock pulse φ1 again, and transfers this count value to the comparator 417. Output to. Therefore, the comparator 417 is the latch circuit 4]
Tempo data and variable clock pulse φ added from 5
A coincidence signal "I" is output at a period corresponding to the period of ".".

The output of the OR circuit 421 is added to the other input of the AND circuit 420. The OR circuit 421 takes the OR condition of the melody match signal MKEQ and the output of the inverter 422 that inverts the stop command signal MP.
When Q and signal MP are respectively shown in FIG. 5(b) and FIG. 5(d), the signal "1" is always output, and the signal M
When KEQ and signal MP are in FIG. 4(b) and FIG.
A signal "1" is output except for the time from the rise of Q to V. That is, the OR circuit 421 detects the normal performance time t
If the actual performance time t KON is earlier than o, the full signal ``'1'' is always output, and if it is later, the signal MP rises (at the time when the third tempo clock is output from the regular performance time io) The signal NOI+ is output from the time tKON to the actual performance time tKON.

The AND circuit 420 becomes operational when the OR condition of the OR circuit 421 is satisfied, and outputs a pulse signal periodically applied from the AND circuit 419 as a gold tempo clock TCL. Of course, when the OR circuit 421 is outputting the signal "0", the generation of the tempo clock TCL is stopped. That is, the output of the OR circuit 421 controls the generation of the tempo clock TCL to be stopped.

Here, when the performance corresponding to the first note of the melody is performed and the melody matching signal MKEQ is output, the differentiation circuit 424 differentiates this signal MKEQ, and at the 9th rising edge of the melody match signal MKEQ is output. Signal latch circuits 413 and 41
Add it to the load terminal LD of No.4. The latch circuit 413 latches the tempo data added from the limiter 416, and the latch circuit 414 latches the debo correction data added from the counter 423. Note that the counter 423 is preset with the tempo data of the reference tempo clock, as described above. Therefore, latch circuits 413 and 41
Both of the tempo data latched at 4 are the tempo data of the reference tempo clock.

On the other hand, when the melody match signal MKEQ is applied to the AND circuit 420 via the OR circuit 421 and the tempo clock TCL is output from the AND circuit 420, the melody data retrieval circuit 100 immediately outputs the melody data read command signal MLU. The read control circuit 18 outputs a next melody read request signal M N Rd. This signal MNR
is applied to the reset terminal R of. This allows the signal M
KEQ becomes "0" and the counter 423 is reset. Further, the melody data extraction circuit 100 outputs melody note length data ML corresponding to the first note of the melody to the variable frequency divider 425.

Variable frequency divider 425ij: input melody note length data M
It divides and outputs the variable clock pulse φ* output from the variable frequency divider 430 with a frequency division ratio corresponding to L, and the period of the clock output from the variable frequency divider 425 is the variable clock pulse φ10F3M. When is constant, it is proportional to the note length indicated by the input melody note length data ML. For example, the period of the clock that is divided and output based on the note length data ML corresponding to a quarter note is twice the period of the clock that is divided and output based on the note length data ML that corresponds to an eighth note. Become.

The variable frequency divider 430 divides the high-speed clock pulse φ by a frequency division ratio corresponding to the data applied from the selector 428, and outputs the divided clock pulse as the variable clock pulse φ''. Either one of the A input and B input is selectively outputted depending on the operating state of the tempo change data STM from the above-mentioned performance level detection circuit 300.
P is added, and to the B input, jyr-ya reference data regardless of performance difficulty level, for example, data indicating a value of 1゛5'' is added from the reference data generation source.

Here, when the selection switch 431 is turned on, a signal "1" is added to the A-person selector Q SA of the selector 428, so the selector 428 selects the A input and changes the tempo being applied to the A input. When the data STMP is output to the variable frequency divider 430 and the selection switch 431 is turned off,
Signal e01 is sent to the A person select terminal SA of the selector 428.
+ is added, the selector 428 selects the B input, and transmits the reference data added to the B input to the variable frequency divider 43.
Output to 0.

The variable frequency divider 430 divides and outputs the high-speed clock pulse φ at a division ratio corresponding to the data applied from the selector 428, as described above, but when the selection switch 431 is turned on, the high-speed clock pulse φ is The frequency is divided and output at a frequency division ratio corresponding to the tempo change data STMP. Note that since the tempo change data STMPt is data that takes a value of "5" to "16" depending on the performance difficulty level, the period of the variable clock pulse φ output from the variable frequency divider 430 when the performance is the most difficult. is approximately three times the period when the performance is the easiest.

The clock output from the variable frequency divider 425 is applied to the clock input CK of the counter 423 via an AND circuit 426. The output of the NAND circuit 427 is added to the other input of the AND circuit 426. The NAND circuit 427 takes the NAND condition of the count value (binary code) output from the counter 423 to the latch circuit 41.4, and outputs a normal signal '°1'' to enable the AND circuit 426 to operate. When all bit outputs become 1''', a signal ``0'' is output to the AND circuit 426 to block output of the clock from the AND circuit 426.

Here, when the performance corresponding to the second note of the melody is performed and the melody match signal MKEQ is output, the latch circuit 4. ] 3 4141-j When this signal MKE'Q rises, it latches the tempo data input to v+11. At this time, the tempo data latched by the launch circuit 414 is the count value of the counter 423, and the value υ,
? ) If the performance time is earlier than the regular performance time, the value will be small, 10, and 9, and if it is later, the value will be large.

Tempo data t latched by the launch circuit 414
, is added to the B input of the arithmetic circuit 412 as tempo correction data.

As described above, the calculation circuit 412 takes the average value of the two-person force data, and outputs this average value f as new tempo data.

In this way, the tempo clock m11 circuit 400t adjusts the tempo clock T according to the playability of the notes to be played.
The frequency of the CL is controlled, and the more sophisticated the performance, the slower the reading speed of the performance data.

Further, if the key press is delayed further than the performance timing according to the performance speed and note length data, generation of the tempo clock TCL is prohibited and the progress of the automatic performance is stopped. Furthermore, the tempo (period of the tempo clock) of the automatic performance is automatically controlled depending on whether the key depression is earlier or later than the performance timing.

Note that the tempo control circuit is not limited to one having the above-mentioned control function, and may be one that generates a tempo clock of a preset frequency and changes the frequency according to the playing difficulty of the note to be played. Any device may be used as long as it can be used and changes the reading speed of the performance data according to the difficulty level of the notes to be played.

In addition, in this embodiment, in order to detect the difficulty level of the performance, four
However, other detectors may be used, such as a detector that detects the difficulty level according to the frequency of appearance of notes to be played in a piece of music. Alternatively, the difficulty level of the performance may be detected by a detector consisting of a combination of a plurality of detectors.

As explained above, according to the present invention, since the speed of automatic performance is changed according to the performance difficulty level of the note to be played,
Even if you come across a difficult part during a performance, you can perform manually according to the progress of the automatic performance.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of an electronic musical instrument to which this invention is applied, and Fig. 2 is an automatic performance data no.
Section 1 is a block diagram showing a detailed example of the melody data extraction circuit according to the present invention; FIGS. 4 and 5 are timing charts of each signal according to the present invention; FIG. 7 is a block diagram showing a detailed example of the reciprocal/obligate data extraction path according to the present invention, FIG. FIG. 2 is a block diagram showing a detailed example of a tempo control circuit according to the invention. ]... Key pasting, 8... Rakuten formation circuit, 10 Speaker, 13... Music data input device, 14... Data memory, 15. RAM IJ' included control circuit, 16. Address counter, 17 ...Start switch, 18...
RAM read control circuit, 19, data output circuit, 20...
・Display device, 100 ・Melody data retrieval circuit, 200
...Chord/obligado data extraction path, 300...
-Performance difficulty level detection circuit, 400...Tempo control circuit. Figure 6 ONR Figure 7

Claims (7)

[Claims] (1) In an electronic musical instrument having an automatic performance device, a storage means for storing data regarding notes to be played on a keyboard, and reading the stored data from the storage means in accordance with the automatic performance tempo of the automatic performance device e; performance difficulty detection means for detecting the performance difficulty level of the note to be played based on the data; and changing the automatic performance tempo of the automatic performance device according to the performance difficulty level detected by the performance difficulty detection means. An electronic musical instrument comprising a tempo changing means. (2) The electronic musical instrument according to claim 1, wherein the automatic performance device includes tempo control means that automatically controls the tempo in relation to the speed and slowness of the performance on the keyboard. (3) The electronic musical instrument according to claim 1, wherein the performance difficulty level detecting means detects the performance difficulty level based on the pitch difference between the currently played note and the note to be played. (4) The electronic musical instrument according to claim 1, wherein the performance difficulty level detecting means detects the performance difficulty level depending on whether the key corresponding to the note to be played is a white key or a black key. (5) The electronic musical instrument according to claim 1, wherein the performance difficulty level detecting means detects the performance difficulty level based on the note length of the currently played note. (6) The electronic musical instrument according to claim 1, wherein the performance difficulty level detecting means detects the performance difficulty level based on the sum of note lengths of a plurality of notes including the note to be played. (7) The tempo changing means divides a high-speed clock pulse forming a tempo clock for controlling the automatic performance tempo of the automatic performance device into a frequency corresponding to the performance difficulty detected by the performance difficulty detection means. D divided by the ratio
An electronic musical instrument according to claim (1), comprising a J-variable variation multiplier.