JPS628797B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument in which keys are functionally divided at arbitrary positions to facilitate performance.

When playing an electronic keyboard instrument, the right hand usually plays the melody and the left hand plays the accompaniment, but the melody in the right hand and the accompaniment in the left hand are often played with different rhythm patterns, and beginners need to know how to calculate them. was difficult.

Therefore, consideration has been made for beginners, such as specifying a chord with one finger of the left hand, and the chord performance is output according to the rhythm pattern of the linked rhythm box, but this method does not have much variation. Moreover, not only the inverted chords written on the score were not pronounced, but also the bass note was uniquely determined.

Additionally, it may be difficult for beginners to keep up with the constant tempo set by the rhythm box, so further improvements have been desired.

The present invention has been made in view of the above circumstances, and it stores and sets both accompaniment and melody in advance, and when playing, divides the functions of the keys at arbitrary positions, and selects any one of the divided keys. An electronic musical instrument that allows you to play a melody simply by playing according to a rhythm pattern, and an accompaniment by simply playing any other key according to a rhythm pattern, making it possible to play even difficult songs with simple performance. The purpose is to provide.

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view of the main body of an electronic musical instrument in this embodiment, and numeral 1 in the figure is a keyboard consisting of four octaves. The keyboard 1 is constructed so that functions can be divided at arbitrary positions, as will become clear from the explanation that follows. Reference numeral 2a is a switch for specifying whether to use the keyboard 1 normally, to use it with divided functions, or to write played information into a first memory or a second memory (described later). Further, 3 is an external operation switch such as a power switch and a volume control, and 4 is a speaker.

Next, the circuit configuration of this embodiment will be explained with reference to FIG. The circuit configuration shown in Figure 2 is roughly divided into five blocks and a circuit that connects each of these blocks, each of which is composed of, for example, one LSI (large scale integrated circuit) or hybrid IC. has been done. That is, 1
0 is a key input section operated by each key of the keyboard 1; 20 is a musical tone generating section composed of a circuit for creating and outputting musical tones, a circuit for controlling key input, etc.;
30 are the first and second pitch codes for which pitch codes are set in advance.
A memory section 40 includes a memory for storing division positions and a control section consisting of a circuit for controlling the memories 31 and 32. 50 is an amplifier.

Each of these blocks 10 to 50 and their connection circuits will be described in detail below.

As mentioned above, the musical tone generating section 20 is provided with a 4-bit note counter 21 and a 2-bit block counter 22 for scanning the keyboard 1 and detecting pressed keys, and the first stage of the note counter 21 has a scanning counter. A clock O/ _A is applied for this purpose. The note counter 21 sends the count contents to the note decoder 23, and the note decoder 23 receives the count value of the note counter 21 from 0 to
11" to the 12 lines 23a to 23l corresponding to the 12 notes "C to B" at different timings, and scan keys with the same note name in each octave of the key input section 10. An output is obtained on the line 23m of the decoder 23 when the counter value of the note counter 21 reaches "12", and this output is applied to the note counter 21 as a reset signal and to the block counter 22 as a counting clock. . The block counter 22 counts according to the counting clock, and its count output is sent to the block decoder 24.
is sent to. The block duder 24 outputs different timing signals to the lines 24a to 24d in accordance with the count value "0 to 3" of the block counter 22, and the signals output to the lines 24a to 24d are outputted to the AND gates 25a to 25 as octave detection signals. 25d, respectively. The outputs of the AND gates 25a to 25d are output from the OR gate 26.
It has a function of serial-parallel conversion via
The data is input to a shift register 27 having a capacity of 48 bits corresponding to the number of keys in the key input section 10. This shift register 27 has a unique bit position for each key in the key input unit 10 and stores information for the pressed key, and its parallel output is composed of 48 bits, which has the same capacity as the shift register 27. is applied to the buffer 28. Batsuhua 28
reads the output of the shift register 27 when all keys in the key input unit 10 have been scanned, and uses line 23m of the note decoder 23 and line 2 of the block decoder 24 as read signals.
The output of the AND gate 28a to which the signal outputted to 4d is applied is applied. The output of the buffer 28 is sent to a tone generation circuit 29 that generates musical tone signals, and the tone generation circuit 29 digitally generates various musical tones in accordance with the pitches of the operated keys. The musical tone signal digitally created by this musical tone creating circuit 29 is outputted via a digital-to-analog converter 29a provided in this musical sound creating circuit 29, and the converted analog signal is sent to an amplifier 50. The sound is amplified and produced by the speaker 4. The operational output of the externally operated switch 3 is applied to the musical tone generating circuit 29, and the musical tone generating circuit 29 generates a predetermined musical tone signal according to the output of the buffer 28 and the operational output of the externally operated switch 3. .

On the other hand, the key input section 10 has a structure in which a diode 12 and a switch 13 interlocked with each key of the keyboard 1 are provided at the intersection of the row line and the column line, as shown in detail by a circle 11. The 48 switches for 4 octaves are arranged in a matrix of 4 rows and 12 columns. That is, each column line of the key input section 10 corresponds to the lines 23a to 23 of the note decoder 23.
l, and on this column line are keys with the same note name but different octaves, and in the same row are keys ``C~
Keys corresponding to the 12 tones of "B" are connected, and key operation outputs can be obtained from the key input section 10 on each line 10a to 10d at the timing of each note name.

Thus, the key operation signals outputted to lines 10a-10d are applied to AND gates 61a-61d, respectively, and the outputs of these AND gates 61a-61d are applied to AND gates 25a-25d, respectively. The opening and closing of the AND gates 61a to 61d are controlled by an output signal A output from a control section 40, which will be described later. That is, the AND gate 61a
~61d are lines 10a~10 of the key input section 10
This controls whether or not the key operation output outputted to d is inputted to the tone generation section 20.

Further, the key operation outputs outputted to the lines 10a to 10d are also inputted to the memory section 30, and the first
AND gate 3 in memory 31 and second memory 32
It is input via 1a to 31d and 32a to 32d. These AND gates 31a to 31d and 3
Opening control signals B and C are applied to 2a to 32d from a control circuit 40, which will be described later, and these control circuits 40
Outputs B and C from the memory 31 and 32 are further applied as read/write signals (R/W) to the memories 31 and 32, respectively. Note that the memory unit 30 includes memories 31 and 32.
The two memories 31 and 32 are provided in order to write both the accompaniment sound and the melody sound respectively by key operation of the key input unit 10, and these memories 31 and 32 are equipped with some additional circuits. It can be made into one thing just by adding .

In addition, signals G and F are input from the control unit 40 to the first and second memories 31 and 32 to increment the address setting circuit provided in these memories and to instruct writing or reading. There is.

The memories 31 and 32 also have lines 23a to 23 from the note decoder 23 as pitch name identification signals.
The note code output to 1 and the block code output from AND gates 31a to 31d or 32a to 32d are written.

On the other hand, the control section 40 controls line 1 of the key input section 10.
A control signal B receives the key operation outputs outputted to 0a to 10d, the clock O/ _A , and the output of the switch 2a, and performs opening/closing control for the AND gates 31a to 31d, 32a to 32d, and write/read instructions to the memories 31 and 32. , C, increment signals G, F for memories 31 and 32,
It outputs the opening/closing control signal E for the AND gates 31e to 31h and the opening/closing control signal D for the AND gates 32e to 32h.
As shown in the figure. Note that the input/output terminals in the detailed view shown in FIG. 3 do not coincide in position with those shown in FIG. 2.

That is, in FIG. 3, 401 and 402 are the note counter 21 and block counter 2 shown in FIG.
Counter 40 is a counter that operates in synchronization with Counter 2.
A clock signal O/ _A similar to the clock signal input to the note counter 21 is applied to the first stage of the note counter 21. Then, when the counter 401 counts "12", the counter 401 counts "12".
The signal output to line 403 resets the counter 40.
It is applied as a counting clock of 2. The output of the counter 402 is input to a key-on detection circuit 404, which converts key operation signals output to lines 10a to 10d of the key input section 10 to AND gates 25a to 25a.
Similarly to 25d, the octave is selected and output, and the output is output via the OR gate 405. Therefore, the output of this OR gate 405 is input directly to AND gates 406 and 407, and to an AND gate 409 via an inverter 408. The AND gate 406 receives the output of the 48-bit capacity shift register 410 from the inverter 4.
The output of the shift register 410 is directly supplied to the AND gates 407 and 409 through 11. That is, these AND gates 406,4
07,409, when a new key operation is performed,
A "1" signal is output when the key operation is continued and when the key operation is stopped. The outputs of the AND gates 406 and 407 are applied to the shift register 410 via the OR gate 412. Further, the output of the AND gate 406 is applied to the AND gate 413 together with the output of the division instruction contact of the switch 2a, and the output of the AND gate 413 is used as a reading command to the memories 414 and 415 that store the contents of the counters 401 and 402. give as. That is, memories 414, 415
When the switch 2a is in the division instruction position, the position of the operated key is determined by the note code and block code by reading the contents of the counters 401 and 402, which operate in synchronization with the note counter 21 and block counter 22. The output is applied to the coincidence circuit 416 along with the outputs of the counters 401 and 402. Matching circuit 41
6 compares the information output from the counters 401 and 402 with the codes output from the memories 414 and 415, and applies the coincidence output to the set terminal S of the R-S flip-flop 417 when they match. The reset terminal R of the R-S flip-flop 417 is connected to the output obtained on the line 418 when the count value of the counter 402 reaches "3" and the output on the line 40.
3 is applied via an AND gate 419. And this R-S
The set side output Q of the flip-flop 417 is applied to AND gates 420 and 421, and the outputs of the AND gates 406 and 409 are applied to the AND gates 420 and 421, respectively. The outputs of AND gates 420 and 421 are applied to set terminal S and reset terminal R of R-S flip-flop 422. In addition, the above R
The reset side output of the -S flip-flop 417 is applied to AND gates 423 and 424, and the outputs of the AND gates 406 and 409 are applied to the AND gates 423 and 424, respectively. And these AND gates 423 and 424
The output of is applied to the set terminal S and reset terminal R of the R-S flip-flop 425.

Further, the set side output Q of the R-S flip-flop 417 is applied to an AND gate 426, and the reset side output is applied to an AND gate 427. The AND gates 426 and 427 are further supplied with the output of the contact point of the switch 2a which instructs reading from the memories 31 and 32, and the output of the AND gate 406. And this AND gate 426
The outputs of 427 and 427 are output from OR gates 428 and 427, respectively.
429.

Furthermore, this OR gate 428 includes a switch 2a.
The output of an AND gate 430 to which the output of AND gate 406 is applied and the output of a contact specifying writing into memory 32 are supplied. Further, to the OR gate 429, the output of the contact point of the switch 2a that designates writing to the memory 31 and the output of the AND gate 406 are applied to an AND gate 4.
31 outputs are provided. Therefore, the outputs of these OR gates 428 and 429 are
2 and 31, are sent as increment signals F and G.

Further, the set side output Q of the R-S flip-flop 422 is connected to the memory 3 of the switch 2a.
It is applied to the AND gate 432 along with the output of the contact specifying the readout from 1 and 32, and its output is
It is supplied as an opening/closing control signal D for the AND gates 32e to 32h. The set side output Q of the R-S flip-flop 425 is applied to the AND gate 433 together with the output of the contact point of the switch 2a which designates reading from the memories 31 and 32, and the output is applied to the AND gates 31e to 31h. It is supplied as an opening/closing control signal E.

Furthermore, the control signal A output from the control section 40
is obtained from the OR gate 434 to which a contact signal designating normal performance of the switch 2a, a contact output commanding writing to the memory 31, and a contact output commanding writing to the memory 32 are applied, and the control signal B , C are respectively composed of the output of a contact point of the switch 2a that instructs writing to the memory 31, and the output of a contact point of the switch 2a that instructs writing to the memory 32.

Next, in the above configuration, for example, the lowest octave of the four octave keys, that is, C ₂ ~
The keys B ₂ (referred to as the first key group 1a for convenience of explanation) are used for reading and playing accompaniment sounds, and the keys C ₃ to B ₅ (referred to as the second key group 1b for convenience of explanation) are used for reading and playing melody sounds. Memories 31 and 32 are used for reading and playing.
The case of reading out the contents of each will be explained with reference to FIG.

First, to indicate the separation position, the switch 2a is set to designate the division position, and the key "C ₃ " is operated in order to use keys C ₂ to B ₂ for reading and playing accompaniment sounds. this
Line 1 of the key input section 10 is activated by operating the key _C3 .
At 0b, an operation output is obtained at timing "C" and is input to the key-on detection circuit 404 of the control section 40. The key-on detection circuit 404 outputs a "1" signal to a predetermined line of the OR circuit 405 based on the contents of the counter 402. As a result, the AND gate 406 outputs a "1" signal, and the AND gate 413 outputs "1", so that the counters 401 and 4 are stored in the memories 414 and 415.
The contents of 02 are read. Therefore, matching circuit 41
From 6 onwards, a coincidence is always detected at timing _C3 during key scanning, and the R-S flip-flop 417 is brought into the set state.

Next, a case will be described in which the accompaniment score shown in FIG. 4 is stored in the first memory 31 and the melody score shown in FIG. 4 is stored in the second memory 32.

First, in order to store the melody score shown in FIG. At this time, the second memory 32 is in a writable state by sending open signals to the AND gates 32a to 32d. So, in order to memorize the first note "G ₄ ", if you operate the "G ₄ " key on keyboard 1, the operation signal will be sent to line 10c as the note timing "G".
, and is applied to the second memory 32 via the AND gate 32c. At this time,
The signal output to the line 10c is output from the OR gate 405 at a timing unique to "G ₄ ",
Since there is no "1" in the bit position of "G ₄ " in the shift register 410 until then, an output of "1" is obtained from the AND gate 406 . Therefore, AND gate 430 satisfies its logical condition, and increment signal F is applied to memory 32 via OR gate 428 as a read command. As a result, the second memory 32 stores lines 23a to 2.
Note code output to 3l and AND gate 3
The block codes output from 2a to 32d are read and stored. Note that the memory 32 (the same applies to the memory 31) counts the number of times the "B" chord is output using the note codes output to the lines 23a to 23l, and scans all the keys from C ₂ to B ₅ . The chords input in between are stored as being to be sounded simultaneously, but currently only the "G ₄ " chord is stored. When the next key operation for "B ₄ " is performed, "B ₄ " is stored in memory by the same operation as described above. Following the melody score shown in Fig. 4, by operating "D ₅ ", "B ₄ ", "D ₅ ", "E ₅ ", etc., the memory 32 will contain the melody as shown in Fig. 4. The indicated melody pattern is stored and set.

Next, to memorize the accompaniment score, switch 2a
Set the pitch code to the position where you want to write it to the memory 31, and operate the keyboard 1 to write the pitch code to the first memory 3.
1. At this time, the first memory 31 is in a writable state by sending open signals to the AND gates 31a to 31d. Therefore,
First, when the key of the first note "G ₂ " is operated, the operation output is outputted to line 10a at the note timing of "G", and the output of this line 10a is applied to the memory 31 via the AND gate 31a. At the same time, note codes output to lines 23a to 23l are applied to memory 31. At this time _{, the signal outputted to the line 10a is outputted from the OR gate 405 at a timing unique to "G 2 "} , and until then, the AND gate 4
A "1" output is obtained from 06. Therefore, the AND gate 431 satisfies the logical condition, and the increment signal G is applied to the memory 31 via the OR gate 429 as a read command. As a result, the memory 31 stores the note codes output to the lines 23a to 23l and the AND gates 31a to 31.
The block code output from d is read and stored. Then, when the keys "G ₃ , B ₃ " are operated next, "G ₃ , B ₃ " are stored as being to be sounded simultaneously by the same operation as described above. Following the accompaniment score shown in Figure 4, "G ₃ , B ₃ ", "D ₃ "
By operating "G ₃ , B ₃ ", "G ₃ , B ₃ ", etc., the accompaniment pattern shown in FIG. 4 is stored and set in the memory 31.

Next, consider only the rhythm pattern of the melody and accompaniment that have been memorized in this way, and for the melody, press any key of the second key group 1b with one finger of the right hand, and for the accompaniment. A case will be described in which a song stored in advance in the first and second memories is played by playing any key of the first key group 1a with one finger of the left hand. In this case, as shown in FIG.
This is the position that specifies reading from. With this setting, the AND gates 61a to 61d are not opened, and the first key group 1a and the second key group 1b are used to play the accompaniment and melody songs stored and set in the first and second memories 31 and 32, respectively. The function is set as a read key. Also, due to the key separation specification mentioned above, at the key timing of C ₂ to _{B 2} , R-S
The reset side output of the flip-flop 417 becomes "1", and the set side output Q becomes "1" at key timings _C3 to _B5 .

When performing the song, since the first two notes of the melody of the song shown in FIG. 4 are without accompaniment, the player operates any key of the second key group 1b with his right hand. As a result of this operation, the output generated on any of the lines 10b to 10d of the key input section 10 is
The signal does not pass through the AND gates 61b to 61d and is supplied to the key-on detection circuit 404. However, at that timing, the set side output Q of the R-S flip-flop 417 is "1" as described above, so the logic condition of the AND gate 420 is satisfied, and the R-S flip-flop 42
2 is set to the set state, and its output is sent as control signal D to AND gates 32e to 32h via AND gate 432.

At the same time, the logic condition of the AND gate 426 is satisfied, and the memory 3
2, an increment signal F is sent. Second
The memory 32 uses the note decoder 23 according to this instruction.
The note code output to the lines 23a to 23l is compared with the note code stored and set in advance, and if a match is detected, the note code is output to the line according to the block code written in advance. In this case, since the pitch stored first in the memory 32 is "G ₄ ", an output is generated on the line applied to the AND gate 25c.

AND gate 25c has a block decoder 24
Since the octave detection signal is applied through the line 24c, when this line 24c is selected, that is, when the count value of the block counter 22 reaches "2", the operation signal "G ₄ " is applied. The data is written into the shift register 27 via the AND gate 25c and the OR gate 26, and thereafter shifted sequentially. Thus, when an output is received from the AND gate 28a, that is, when all keys of the key input section 10 have been scanned, the signal input to the shift register 27 is read into the buffer 28, and the musical tone creation circuit 29 is transferred to the buffer 28. A musical tone with a pitch of "G ₄ " is created according to the data read in, and is sounded by the speaker 4.

Then, when the right-hand key operation is stopped, at that timing, the AND gate 409 outputs a "1" signal, and since the R-S flip-flop 417 is in the set state, the AND gate 42
1, a reset signal will be sent to the R-S flip-flop 422. Therefore, the set side output Q becomes "0", the opening signal is no longer supplied to the AND gates 32e to 32h, and the sounding of the musical tone "G ₄ " is stopped.

Next, in order to output the second note of the melody, when any key of the second key group 1b is operated, the musical tone creation circuit 29 generates a musical tone with a pitch corresponding to "B ₄ " by the same operation as described above. is created and pronounced.

Then, in order to output the next melody sound, the second
When playing the key group 1b, the user plays any key in the second key group 1b with the right hand, and also plays any key in the first key group 1a with the left hand in order to output an accompaniment sound. As a result, the sound generation based on the operation output of the second key bullet 1b is the same as above, but when a predetermined key of the first key group 1a is operated, the R-S flip-flop 417 is reset at that timing. Therefore, the logic condition of AND gate 423 is satisfied, R-S flip-flop 425 is set, and its output is passed through AND gate 433 to AND gate 3.
The opening signal E is sent to 1e to 31h.

At the same time, the logical condition of the AND gate 427 is satisfied and an increment signal G is sent to the memory 31. Based on this instruction, the first memory 31 compares the note code output to the lines 23a to 23l of the note decoder 23 with the note code stored and set in advance, and if a match is detected, the first memory 31 follows the pre-written block code. Output to the ivy line. In this case, the pitch stored first in the memory 31 is "G ₂ ", so when the note code "G" is output to lines 23a to 23l, no output is obtained from the memory 31. , is applied to the AND gate 25a. Therefore, the musical tone generating circuit 29 simultaneously generates two tones "G ₂ " and "D ₅ " and outputs them through the speaker 4. and,
When the left-hand key operation is stopped, the AND gate 409 outputs a "1" signal at that timing, and since the reset side output of the R-S flip-flop 417 is "1", the AND gate 4
24, a reset signal is sent to the R-S flip-flop 425. Therefore,
The set side output Q becomes "0", the opening/closing control signal E of the AND gates 31e to 31h becomes "0", and the sounding of the musical tone "G ₂ " is stopped.

Hereinafter, the right hand will play any key in the second key group 1b according to the rhythm shown in the rhythm score in Figure 4, and the left hand will play the first key in accordance with the rhythm shown in the rhythm score in Figure 3.
By playing any key in key group 1a,
The musical tone generating circuit 29 generates musical tones having pitches corresponding to the musical score shown in FIG. 4, and outputs them through the speaker 4.

In the above embodiment, the first and second key groups were made into one octave and three octaves, respectively, but this division can be performed at any position and is not limited to the above embodiment.

As explained in detail above, the electronic musical instrument according to the present invention stores and sets both accompaniment and melody in advance, and when reading them out, selects one of the two key groups whose functions are divided at an arbitrary position. By playing according to the rhythm pattern of the accompaniment and melody, even difficult songs can be played with simple operations, which is not only effective for beginners, but also allows you to play difficult songs with simple operations. It has various advantages such as being able to play the songs exactly as they are played.

[Brief explanation of the drawing]

The accompanying drawings show an embodiment of the present invention, in which FIG. 1 is an external perspective view of the main body of an electronic musical instrument, FIG. 2 is a circuit block diagram, and FIG. 3 is a detailed view of the control section of FIG. 2.
FIG. 4 is a diagram for explaining the operations of FIGS. 2 and 3. DESCRIPTION OF SYMBOLS 1...Keyboard, 2a...Switch, 20...Musical sound generation section, 30...Memory section, 40...Control section, 4
14,415...memory, 416...matching circuit.

Claims (1)

[Claims] 1 A keyboard, a setting means for setting manual performance, memorized performance, set for memorized performance, and division position designation for memorized performance based on the operational output of the keyboard, and a setting means for specifying division positions for memorized performance by the setting means. a division position storage means for storing the division position by operating the keyboard when specified settings are made; and an accompaniment pitch code input by operating the keyboard when the set for memorized performance is set by the setting means. a first memory for storing the pitch code of the melody inputted by operating the keyboard, and a second memory for storing the pitch code of the melody inputted by the operation of the keyboard; An electronic musical instrument comprising means for setting both keys to function as keys for instructing reading of pitch codes stored in the first or second memory, respectively.