JPS5957344A - レジスタ制御方式 - Google Patents
レジスタ制御方式Info
- Publication number
- JPS5957344A JPS5957344A JP57145961A JP14596182A JPS5957344A JP S5957344 A JPS5957344 A JP S5957344A JP 57145961 A JP57145961 A JP 57145961A JP 14596182 A JP14596182 A JP 14596182A JP S5957344 A JPS5957344 A JP S5957344A
- Authority
- JP
- Japan
- Prior art keywords
- register
- multiplier
- load
- sign bit
- input operand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49994—Sign extension
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Executing Machine-Instructions (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145961A JPS5957344A (ja) | 1982-08-23 | 1982-08-23 | レジスタ制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57145961A JPS5957344A (ja) | 1982-08-23 | 1982-08-23 | レジスタ制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5957344A true JPS5957344A (ja) | 1984-04-02 |
| JPS6235691B2 JPS6235691B2 (enExample) | 1987-08-03 |
Family
ID=15397016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57145961A Granted JPS5957344A (ja) | 1982-08-23 | 1982-08-23 | レジスタ制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5957344A (enExample) |
-
1982
- 1982-08-23 JP JP57145961A patent/JPS5957344A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6235691B2 (enExample) | 1987-08-03 |
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