JPH0239810B2 - - Google Patents

Info

Publication number
JPH0239810B2
JPH0239810B2 JP59064893A JP6489384A JPH0239810B2 JP H0239810 B2 JPH0239810 B2 JP H0239810B2 JP 59064893 A JP59064893 A JP 59064893A JP 6489384 A JP6489384 A JP 6489384A JP H0239810 B2 JPH0239810 B2 JP H0239810B2
Authority
JP
Japan
Prior art keywords
register
bit
bits
storage means
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59064893A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60207929A (ja
Inventor
Yasuhiko Ibuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59064893A priority Critical patent/JPS60207929A/ja
Publication of JPS60207929A publication Critical patent/JPS60207929A/ja
Publication of JPH0239810B2 publication Critical patent/JPH0239810B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
JP59064893A 1984-03-31 1984-03-31 除算制御方式 Granted JPS60207929A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59064893A JPS60207929A (ja) 1984-03-31 1984-03-31 除算制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59064893A JPS60207929A (ja) 1984-03-31 1984-03-31 除算制御方式

Publications (2)

Publication Number Publication Date
JPS60207929A JPS60207929A (ja) 1985-10-19
JPH0239810B2 true JPH0239810B2 (enExample) 1990-09-07

Family

ID=13271213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59064893A Granted JPS60207929A (ja) 1984-03-31 1984-03-31 除算制御方式

Country Status (1)

Country Link
JP (1) JPS60207929A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0302926B1 (en) * 1987-02-24 1993-07-14 Digital Equipment Corporation Control signal generation circuit for arithmetic and logic unit for digital processor
JP4510253B2 (ja) * 2000-08-28 2010-07-21 パナソニック株式会社 演算処理装置

Also Published As

Publication number Publication date
JPS60207929A (ja) 1985-10-19

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