JPS595624A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To anneal a damage given to an ion implantation layer effectively by forming a slender Al pattern as a mask onto a base body and scanning and radiating laser beams in the orthogonal direction to the longitudinal direction. CONSTITUTION:An Al film combining protection against laser annealing is formed to a gate section 15, a gate electrode 15' is formed, and an oxide film 4' made of thin SiO2 is removed while using the Al as a mask. Ions are implanted into the region from an upper section through self-alignment, and the ion implantation layers 3' of source-drain are formed. The whole transistor region is scanned continuously in the direction orthogonal to the side in the longitudinal direction of the gate electrode 15' by a YAG laser. The Al protective film 15' is protected from laser beams because it reflects laser beams. Accordingly, no gate region of the lower section of the Al protective film 15' is affected by such laser beams, but residual regions, the ion implantation layers 3' as source-drain, are irradiated by laser beams and annealed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which an ion implantation portion is laser annealed using an A-pattern mask.

(2) Technology background In recent years, various products that have begun to be widely used in daily life, such as calculators, digital watches, various household electrical appliances, and automobiles, etc.]C are cost reductions due to recent developments in manufacturing technology.
Due to higher density, higher performance, etc., its uses are expanding more and more.

With the development of these manufacturing techniques, various developments have been made in the aforementioned high-density semiconductor devices, and at the same time, the demand for higher performance has also increased.

(3) Prior Art and Problems Typical manufacturing processes for conventional MO3 integrated circuits include, for example, the A-gate structure and the 3i-gate structure.

In the former manufacturing process, as shown in FIGS. 1(8) to (dl), a field inversion prevention layer (encircle) is first formed, and then an oxide film, such as S1O22, is formed to a predetermined thickness on the P-type semiconductor substrate 1. Source , a hole is made in 5iO22 to form a drain region.Next, using 5iO22 as a mask, an n-type impurity 3 is added.
to spread the word. ((a) in the same figure) Next, the thick oxide film 5i022 is removed from the semiconductor formation region, and a new thin gate oxide film 4 is grown.

((b) in the same figure) Furthermore, holes are made in the regions that will become the source and drain. (
(C)) Next, a metal thin film (text A) 5 is deposited and patterned to form the source 6, gate 7, and drain 8 electrodes. (
(d) of the same figure) The latter manufacturing process is as shown in FIG. After removal and opening a window using 5iO22' as a mask, a thin gate oxide film 4' is grown. (Figure (a)) After that, a gate portion is formed using polycrystalline silicon 9. (Figure (b) )) Next, the thin oxide film is removed using the gate portion made of polycrystalline silicon 9 as a mask, and ions of, for example, n-type impurities are implanted or diffused from above.Then, source and drain regions 3' are formed using this n-type impurity. (Figure (C)
) Next, a thick oxide film 10 is grown by, for example, vapor phase growth, and holes for source and drain electrodes are formed.

((d) in the same figure) For example, a metal evaporation of A-cross 11 is carried out and patterned, and the source and drain electrodes 12, 13 and above, the A-gate, and the St-gate all have defects. In other words, in the former case, the A-type electrode cannot withstand the high-temperature treatment required to form the source and drain, so it is difficult to form the source and drain in self-alignment as in the case of the St gate structure, so the n-type source and drain are difficult to form. The gate electrode portion regions 31 and 32 that overlap the regions need to be formed wide by an alignment margin of about 1.5 μm, for example, and are therefore unsuitable for increasing the density of semiconductor devices.

In addition, the latter is a gate electrode region S1. which overlaps the source and train regions as shown in FIG. S2
For example, it has a thickness of about 0.5 μm and is suitable for high-density applications, but since the gate portion is made of polycrystalline silicon, it has high resistance and has the disadvantage of slow operation speed.

In order to eliminate the high resistance that occurs when polycrystalline silicon is used as a gate mask as in the conventional example shown in FIG. 2, it is conceivable to use pattern A as a mask as shown in FIG. 1. Source in this case.

If laser annealing is performed after ion implantation to create the n-type diffusion layer of the drain, the heat generation in the silicon part will be large due to the high reflectivity of the laser beam for pattern A.
Furthermore, the generation of heat in the electrode portion can be reduced. However, at this time, for example, if the laser beam is irradiated in a meandering manner in the longitudinal direction of the A-mask pattern, the laser light will irradiate the sides of the A-mask pattern for a long time, so the heat generated in the silicon part will be transferred. As a result, the sides of the A-pattern may melt and the shape of the pattern may collapse, or in extreme cases, a short circuit may occur between the gate and the substrate. It has been found that the problem of the upper part (B) is not noticeable when the pattern width of the pattern (A) is 4 μm or more, but becomes a serious problem with a narrower pattern.

(4) Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides an ion-implanted layer by scanning and irradiating a laser beam without causing damage to the part that requires maskability, which is made of an aluminum pattern with a width of 4 μm or less. The purpose of this invention is to provide a method for effective annealing for damage sustained by

(5) Structure of the Invention The above object of the present invention is to form an elongated aluminum (A) pattern as a mask on a substrate, and scan a laser beam orthogonally to the longitudinal direction of the A pattern. This is achieved by providing a method for manufacturing a semiconductor device, which is characterized in that hair annealing is performed on a substrate by irradiation.

(6) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 (al to (81) are manufacturing process diagrams of the MO3 semiconductor device of the present invention.

After forming a field inversion prevention layer (surrounding circuit) on the P-type substrate 1', the thick oxide film 2' made of, for example, 5i02 in the transistor region 14 is removed, and a thin gate oxide film 4' made of, for example, 5i02 is formed thereon. Let it grow again. (Same figure (a)
l) Next, an A pattern film that also serves as protection against laser annealing, which is a feature of the present invention, is formed on the gate portion 15, and the gate electrode 15 is
'make. (Figure (b)) Using this pattern A as a mask, the thin SiO2 oxide film 4' is removed. Ion implantation is performed in this region from above in a self-aligned manner, for example, to form source and drain ion implantation layers 3'. ((C) of the same figure) Here, in order to remove damage during ion implantation, for example, the output is set to 0.
35W, pulse 5KHz, 20μ/5tep
At the cavity, a YAG (yttrium aluminum garnet) laser is used to continuously scan 18 the entire transistor region 14 in a direction perpendicular to the longitudinal sides of the gate electrode 15', as shown in FIG. In this case, if the gate electrode pattern is bent in an L-shape as shown in Figure 4, annealing can be performed without any particular problem even if the short side 15a is 4 μm or more, even if the gate electrode pattern is scanned along the longitudinal direction. . In other words, in the case of a thick pattern of 4 μm or more, even when scanning along the longitudinal direction, the heat transmitted from the silicon part is diffused not only in the longitudinal direction but also in the lateral direction to a considerable extent. This is because the temperature rise at the end of the tube can be suppressed.

In this case, A also protects 1! The surface of t15' is formed by humanities and is protected from the laser beam because it reflects the laser beam. Therefore, the gate region under the A-supporting protective film 15' is not affected by the laser beam at all, but the remaining region, that is, the ion-implanted layer 3' which becomes the source and drain, is irradiated with the laser beam and annealed. . Typically, implanted ions collide with atoms in the lattice, displacing them from lattice points, before losing their kinetic energy. As a result, many vacancies are generated and the layer changes to an amorphous layer or the like. Therefore, it is necessary to perform annealing after ion implantation to restore the crystal structure. Anneal the source of the ion implantation layer.

The specific resistance of both the drain parts is reduced and the operational function as a transistor is restored. Next, by vapor phase growth method, for example, 3i0
A thick oxide film 10' of source 16.2 is grown. Drill a hole for the drain 17. ((d) in the same figure) On top of this, metal is deposited using, for example, A or the like, and patterned to form source and drain electrodes 12'.

Make 13'. ((e) in the same figure) That is, according to the present invention, an ion-implanted layer 3' serving as a source and a drain is provided in the transistor region 14 in the field inversion layer on the semiconductor substrate 1, and an insulating layer 4 is provided in the center. ' is formed, and furthermore, an A-supporting protective film 15' of the gate portion, which is a feature of the present invention and serves as a protective film during laser annealing, is provided on the A-supporting film 15', which protects the A-supporting film from being irradiated with laser light during laser annealing. Since the laser power is applied in a direction almost perpendicular to the long side of the film 15', the side of the A-supporting protective film 15' receives less laser power, so this side does not melt.On the other hand, the laser power is effective for the source and drain regions. Laser power sufficient to perform annealing can be provided.

As mentioned above, the present invention has been described for the case where it is applied to laser annealing in an MO3 semiconductor device, but it can be used for any purpose other than the above as long as laser irradiation is performed selectively by masking A or the like. It is.

(7) Effects of the Invention The present invention is applied, for example, in a semiconductor device manufacturing process, by using an A or metal thin film as a selective mask and scanning and irradiating the A or metal thin film pattern with a laser beam at an angle of about 90'. This enables good self-alignment and shortens the gate-source and gate-drain overlap regions S1 and S2, making it possible to increase the density of transistors and ultimately shorten the gate width. In addition, since the gate part uses A pattern with high electrical conductivity, the resistance of the gate part can be kept low, and the laser power is stronger than when laser annealing is performed along the A pattern metal thin film pattern. The source,
It has a feature that the resistance of the drain can be lowered, and therefore the operating speed of the transistor can be increased.

[Brief explanation of drawings]

Figures 1 (a) to (d) are manufacturing process diagrams of a conventional MO3 semiconductor device with an aluminum gate structure, and Figures 2 (al to (e) are the same) (manufacturing process diagrams of a conventional MO3 integrated device with a silicon gate structure) , Fig. 3 (al to e) are process diagrams of an MO3 semiconductor device incorporating the semiconductor of the present invention, and Fig. 4 is a route diagram explaining the scanning method on the A pattern mask of the present invention. 1.1 '... P-type substrate, 3... Ion implantation layer (gas diffusion layer), 4.4'... Gate oxide film, 5.
...metal thin film, 6,16...source, 7...
Gate, 8.17...Drain, 9...Polycrystalline silicon, 12...Source electrode, 13.
...Drain electrode, 14...Transistor region,
15'...A gate electrode.夙 2I2Il Figure 3-18 ) 〉 )

Claims (1)

[Claims] Manufacture of a semiconductor device characterized by forming an elongated aluminum (A-shaped) pattern as a mask on a substrate, and performing hair annealing on the substrate by scanning and irradiating laser light perpendicular to the longitudinal direction of the A pattern. Method.