JPS5946095A - Method of producing conductor circuit for printed circuit board - Google Patents
Method of producing conductor circuit for printed circuit boardInfo
- Publication number
- JPS5946095A JPS5946095A JP15609482A JP15609482A JPS5946095A JP S5946095 A JPS5946095 A JP S5946095A JP 15609482 A JP15609482 A JP 15609482A JP 15609482 A JP15609482 A JP 15609482A JP S5946095 A JPS5946095 A JP S5946095A
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- base
- circuit
- conductor circuit
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はプリント回路用導体回路の用遣方iz’:、
DC関i シ、Illに’FI7気メッキ処Jjljに
より回路パターンケ形成するフルアディティブ法に卦回
るインナーリード、及びアウ々−リードのl!J 、i
7iカ法に係、イ、。f1Y来のフルアディティブ法に
おHるフリント回路用1導
根から突出する事が出来なかったたk)良い製,遣方法
であったフルアディティブ法がP’f及(ながー)/.
−1。[Detailed Description of the Invention] The present invention provides a method for using conductor circuits for printed circuits.
In DC, the circuit pattern is formed using the FI7 plating process using the full additive method for inner leads and outer leads! J,i
Regarding the 7i law, I. It was not possible to protrude from the first conductor for the flint circuit in the full additive method since f1Y.
-1.
本発明は上述欠点を一掃すべくトロまたものである。J
,ソ下図面とともに本発明の\11b角例V(つい−C
計則に説明する。The present invention seeks to eliminate the above-mentioned drawbacks. J
, \11b corner example V of the present invention together with the drawings below
Explain the rules.
第1図は本発明のプリント回路用導体回路の穴抜きlf
Q[、たベース基鈑を示す略図で、イ121ソ1p−し
。Figure 1 shows the hole punching lf of the conductor circuit for printed circuits of the present invention.
Q[, A schematic diagram showing the base board, I121S1p-.
電気メッキ法により形成した導体回路パターン不、ベー
ス基鈑に接着転写し1c略し1で、第6図rat本発明
[、r.り製造されたプリント回路板用導体回路のイン
ナーリード部分を示す略し1である。A conductive circuit pattern formed by electroplating is adhesively transferred onto a base plate, and the pattern shown in FIG. This is an abbreviation 1 showing the inner lead portion of a conductor circuit for a printed circuit board manufactured by the above method.
第1図に示すごとく、ベース枦1a.VCOールコータ
ーで接着剤を均一に塗布し、プリベーク介L、接着剤を
乾燥させf?:、後、プレスによりブリッナのための穴
2をあけて、転写補強のための島1bをも形成する。次
に、別に電気メツキ法によシ形成した導体回路パターン
6を、第1図のベース基板の上に被せ、力l′l熱し導
体回路パターンろを、ベース先物1aに転写接着(第2
図)する。次に転写接着された導体回路パターン3’i
、プレスにより軒耳補強のたり〕の島1bを切断し、島
1bを取り除き導体回路パターン3をベース基e i
aがら突出させる。As shown in FIG. 1, the base lever 1a. Apply the adhesive evenly with a VCO coater, pre-bake and dry the adhesive. : After that, a hole 2 for the blister is made by pressing, and an island 1b for reinforcing the transfer is also formed. Next, a conductive circuit pattern 6, which was separately formed by electroplating, is placed on the base substrate shown in FIG.
Figure). Next, the conductive circuit pattern 3'i is transferred and adhered.
, cut the island 1b of the eaves sill reinforcement by pressing, remove the island 1b and attach the conductor circuit pattern 3 to the base base e i
Make it stick out from a.
本発明は以上詳述した如く製造されるので、従来フルア
ディティブ法の欠点であったインナーリードやアウター
リードが出来ないという事象を解消し、集積回路の搭載
が簡単になる。Since the present invention is manufactured as described in detail above, it solves the problem of the inability to form inner leads and outer leads, which was a drawback of the conventional fully additive method, and simplifies mounting of integrated circuits.
第1図は本発明のプレス穴抜きされたフリント回路板用
導体回路の支持母体となるベース基板を示す平面略図で
7i!、 2図は、ベース基板に転写接着を施した平
面略図で、第3図は本発明によシ製造されたプリント回
路用導体回路の平面略図である。
1a・・・ベース基板
1b・・・島
2・・・・・・穴
5・・・・・・34 体回路パターン
Jリ −1
出願人 株式会社 即二希T舎
代理人 弁理士 五(11化
y+図
11)3
弔3図FIG. 1 is a schematic plan view showing a base substrate that serves as a support base for a conductor circuit for a flint circuit board having press holes punched therein according to the present invention. , 2 is a schematic plan view of a base substrate subjected to transfer adhesion, and FIG. 3 is a schematic plan view of a conductor circuit for a printed circuit manufactured according to the present invention. 1a...Base board 1b...Island 2...Hole 5...34 Body circuit pattern Jli-1 Applicant Sokunikki Tsha Co., Ltd. Agent Patent attorney Go (11) y + Figure 11) 3 Funeral 3 Figure
Claims (1)
路用導体回路の製造方法において、プリント回路用導体
回路のベース基板に接着層を施し7、プレス等によりこ
のベース基根全穴抜きする工程ど、別に1(イ気メッキ
法により導体回路パターンを形成し、この導体回路パタ
ーンを前述の穴抜きしたベース基’#ii K接着転写
し、導体回路パターンの一部をブリツチ状にする工程と
、ブリッヂVこなった導体回路パターンの片側のベース
基板をプレス等により切断し、導体回路パターンをベー
ス基板から突出させる工程とを有するグ11ント回路鈑
用導体回路の製造方法。In the method for manufacturing a conductor circuit for a printed circuit formed by circuit pattern lJ & air plating, there is a separate step (1) of applying an adhesive layer to the base substrate of the conductor circuit for a printed circuit 7, and punching out all holes at the base of the base by pressing or the like. A process of forming a conductor circuit pattern by the hot plating method, transferring the conductor circuit pattern to the above-mentioned punched base plate with K adhesive, and making a part of the conductor circuit pattern into a brittle shape. A method for producing a conductive circuit for a glued circuit board, comprising the steps of: cutting one side of the base substrate of the conductive circuit pattern with a press or the like, and causing the conductive circuit pattern to protrude from the base substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15609482A JPS5946095A (en) | 1982-09-08 | 1982-09-08 | Method of producing conductor circuit for printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15609482A JPS5946095A (en) | 1982-09-08 | 1982-09-08 | Method of producing conductor circuit for printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5946095A true JPS5946095A (en) | 1984-03-15 |
Family
ID=15620173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15609482A Pending JPS5946095A (en) | 1982-09-08 | 1982-09-08 | Method of producing conductor circuit for printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5946095A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01156482A (en) * | 1987-12-11 | 1989-06-20 | Mitsubishi Cable Ind Ltd | Method for etching superconductor |
JPH06112353A (en) * | 1991-01-04 | 1994-04-22 | Hitachi Chem Co Ltd | Manufacture of substrate fitted with lead for mounting semiconductor |
CN105047598A (en) * | 2015-06-23 | 2015-11-11 | 上海东煦电子科技有限公司 | Membrane pasting method for PCB substrate cutting technology |
-
1982
- 1982-09-08 JP JP15609482A patent/JPS5946095A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01156482A (en) * | 1987-12-11 | 1989-06-20 | Mitsubishi Cable Ind Ltd | Method for etching superconductor |
JPH06112353A (en) * | 1991-01-04 | 1994-04-22 | Hitachi Chem Co Ltd | Manufacture of substrate fitted with lead for mounting semiconductor |
CN105047598A (en) * | 2015-06-23 | 2015-11-11 | 上海东煦电子科技有限公司 | Membrane pasting method for PCB substrate cutting technology |
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