JPS5946054A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS5946054A
JPS5946054A JP57156416A JP15641682A JPS5946054A JP S5946054 A JPS5946054 A JP S5946054A JP 57156416 A JP57156416 A JP 57156416A JP 15641682 A JP15641682 A JP 15641682A JP S5946054 A JPS5946054 A JP S5946054A
Authority
JP
Japan
Prior art keywords
integrated circuit
wire
semiconductor integrated
wires
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57156416A
Other languages
English (en)
Inventor
Yoshimi Marui
丸井 義美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57156416A priority Critical patent/JPS5946054A/ja
Publication of JPS5946054A publication Critical patent/JPS5946054A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
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    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
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    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/4556Disposition, e.g. coating on a part of the core
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
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    • H01L2224/4554Coating
    • H01L2224/45599Material
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    • H01L2224/4805Shape
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
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    • H01L2224/85909Post-treatment of the connector or wire bonding area
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体集積回路装置製造工程中のスクライブ後
の集積回路チップのポンディングパッドとリードフレー
ムを接続するワイヤの絶縁性、信頼性を確実なものとす
るためワイヤの表面に絶縁膜が形成された半導体集積回
路装置に関するものである。
従来、この棟の半導体集積装置装#における集積回路チ
ップとリードフレームケ接続するワイヤは、主として絶
縁被膜ケ持たない金線、アルミニウム線が使用されてい
た。
この場合、モールド金型中での溶融プラスチックの出入
に従ってワイヤ間のショートが発生したり、ワイヤのポ
ンディング後の形状の不都合さが原因で集積回路チップ
のスクライブエツジにシ。
−卜するいわゆるエツジタッチが発生し、てリーク電流
が流れて絶縁不良となったり、例え良品であっても信頼
性′fr、+)4つてし“まうという欠点があった。
また上記方法でワイヤボンティング−する、y、’、 
@[は集積回路チップ上のボンティングパッド位置やリ
ードフレームの設M1には、細かい股引基準の遵守が必
要となり、設計の自由度ゲ著しく減少させていた〇 本発明の目的は従来の絶縁被膜のないアルミニウム線で
集積回路チップのボンティングパッドとリードフレーム
間全ボンディングで接続し、このアルミニウム線を例え
ば陽極酸化してアルミニウム線表面にアルミナの絶縁膜
を形成することに依つて、上記欠点の解決方法の1つを
提供することにある〇 さらに今後の集積回路チヴプ面檀の増加に伴ない多端子
化がさらに進み、ボンティングパッドも多くなり、ワイ
ヤ間隔も著しく狭くなるのでワイヤへの絶#、膜形成は
不可欠のものとなる。
従来の絶縁膜がないワイヤ全使用した場合VCはワイヤ
間のショートやワイヤと集積回路チップのスクライブエ
ツジにショートする不良が少なからず発生した〇 本発明に依ればアルミニウム線を集積回路チ。
プのボンティングパッドとリードフレーム間にポンディ
ングしこのアルミニウム@をシュウ酸溶液中に浸し、電
源の陽極、陰極のそれぞれにリードフレーム、シュウ酸
溶液!極を接続し電流を流すことに依りアルミニウム線
表面にアルミナ膜が形成され1絶縁膜を有するワイヤが
実現出来る。
次1cX発明の実施例について図面を参照して説明する
第1図はベースリボンのアイランド2上[集積回路チッ
プ1ケ、ダイボンディング1、ワイヤボンダにてアルミ
ニウム線5で集積回路チップ1上のポンディングパッド
4とベースリボンのリードフレーム6を接続した従来の
半導体集積装置の部分断面図である。
第2図は第1図に示した従来の半導体集積装置の上、上
音反転させ、シュウ酸溶液7の甲にアルミニウム線5と
集桓回路チッグ1 v)表i*i k 没して11を諒
8の陽極をリードフレーム6(リードフレーム6とアイ
ランド2はベースリボンとして一体となっている金属導
体である)に、他方の陰イ命ケシーウ酸溶液7の!極に
接続して7’、915?lの箱、流、ゲlliずとアル
ミニウム線5のシュウ酸溶液7に接する部分の表面は陽
極酸化によりアルミナ膜が形成される。
第3図は駆2図で説明した方法によりアルミニウム線5
の表面に形成されたアルミナ膜10ケ示す図である〇 このようにして形成したアルミナ膜はアルミニウム線の
艮好な絶縁被膜となり、アルミニウム線間のショートや
第4図に示すようにアルミニウム線5の形状の不都合に
よってアルミニウム線5と集積回路チヅプ1が接触(エ
ツジタッチ)してもアルミナ膜10によってシせ−トケ
防止することが可能となる。
本発明は以上説明したようにアルミニウム線の表面にア
ルミナ膜な形成することによって多端子配線を容易に実
施小米る効果がある。また、モールドパッケージを例に
説明したがセラミックツク、ソケージでも同様の効果が
あることばいうまでもな
【図面の簡単な説明】
第1図は従来の半導体集積装置の部分断1酌図1、第2
図に本発明のアルミニウム線の表向にアルミナ膜を形成
させる笑施例會示す部分断面図、第3図は、アルミニウ
ム線の表面にアルミナ膜力ぶ形成された半導体集積装置
の部分断面図、第4図はアルミナ膜を有するアルミニウ
ム線カニエツジタッチを起こした半導体集積装置の部分
断面図、である。 なお各図において、1・・・・・・集積回路チップ、2
・・・・・・ベースリボンのアイランド、計・・・・・
ノくツシペーション膜、4・・・・・・ボンティングパ
1.Jト、5・・・・・・アルミニウム線、6・・・・
・・ベースリボンのリー ドフレーム、7・・・・・・
シュウ酸溶液、8・・・・・・市、源、9・・・・・・
シュウ酸溶液容器、10・・・・・・fルミツー++q
、 II・・・・・・スクライブエツジ、である。

Claims (1)

  1. 【特許請求の範囲】 外部リードと半導体チップのボンティングパ。 ド間がアルミニウム線で接続された半導体集積回路装置
    において、該アルミニウム線表面にアルミナ膜を含む絶
    縁膜が設けられていることを特徴とする半導体集積装置
JP57156416A 1982-09-08 1982-09-08 半導体集積回路装置 Pending JPS5946054A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57156416A JPS5946054A (ja) 1982-09-08 1982-09-08 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57156416A JPS5946054A (ja) 1982-09-08 1982-09-08 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPS5946054A true JPS5946054A (ja) 1984-03-15

Family

ID=15627270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57156416A Pending JPS5946054A (ja) 1982-09-08 1982-09-08 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS5946054A (ja)

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