JPS5945691A - Access circuit of dynamic memory - Google Patents

Abstract

PURPOSE:To perform real-time control over contention between read/write operation and refreshing operation, by controlling a signal output gate through an RS type flip-flop. CONSTITUTION:The output of the acceptance gate 63 of an NAND gate forming the RS type FF drops to a low level in response to a read/write request signal sent from a CPU1 through the inverter 61 of a contention control circuit 6. Its output is impressed to the set terminal S of the selecting RS type FF65 of the next stage and an AND gate 66 is opened by a high-level output from a terminal ''O'' of the FF65 to output a read/write signal. In this state, when a refresh request signal which does not synchronize with the read/write signal is applied from a refresh signal generating part 2, the reset terminal R of the FF65 drops to the low level and the output of the FF65 does not vary and an AND gate 67 is closed, so that the refresh signal is not generated until the read/ write request signal is disappeared. This constitution performs the control over the contention between the read/write operation and refreshing operation on real-time basis and a CPU operating speed is not reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an access circuit that controls competition between a refresh operation and a read/write operation in a dynamic memory, such as a dynamic F+AM.

Conventionally, there was a device shown in FIG. 1 as this 81 device.

In the figure, (1) is a CPU unit that performs read/write operations on the dynamic memory (5), and (2) is a CPU unit that periodically reads and writes data in the dynamic memory (5).
(3) a competition control unit that performs competition between these read/write operations and refresh operation requests; (4)
is a clock generation section that generates a clock for detecting each operation request for the competing side ri[t1 section (3), and is a part of the dynamic memory as a memory of the +51 id CPU section (1).

Next, the operation shown in FIG. 1 will be explained using the timing chart shown in FIG. The 1'' operation request for the dynamic memory part (5) is a read/write (R/W)! 1TIII operation request by the CPU section (11) and a refresh (REF) operation by the refresh signal generation M1 tatami 2. Request (Dynamic memory (5) is periodically refreshed, otherwise the stored data will be lost)
The two errors occur asynchronously.

Now, at time t1, the CPU section (R/m operation from 11'>
? If a request for assistance occurs (assuming that no request for refretsunyu assistance has occurred at this time), the request IS (rF, 2
ill (b) 1. Pass through the R/W reception gate C3υ of the contention control unit (3) and enter the IIDI+1 child of the R/'W flip-frog (hereinafter referred to as RAV -4-) 0 to 1. The clock signal (21st mesh 1(a)) output from the clock generator section (4) rises at timing t2.
Do the same 1υ1 and P! /! J, FT I-7 function is set No. 1, No. 11111) Terminal j Re-R/W start'i No. (Z2: nl (c)) Force output is 1. Note that this RAI; F7i' I:+2+
The output of 11υII, N:M p is RTI;
When F Ob is set to '5', the subsequent refresh operation request is blocked by this gate Ω1 with I'1EF-Z, and is kept waiting until It/W FFθ,b is reset. R, /'W FF The R/V start signal output from C4Zl is input to the dynamic memory part (5), and upon receiving the signal from the dynamic memory part (51), the read/write operation is executed. 7, when it is completed, at the completion timing t3, 1 (β end signal (second section 1 (d)) is generated, and RAV FF (2
), and also resets the read/write operation request of the CPU section 111. At this time, if the refresh operation request signal (Fig. 2(e)) is being waited for,
RKF-F synchronizes with falling timing t4 of the clock signal immediately after R/W FF ue is reset.
F- is set, and the REF start signal (Fig. 2 (f)) is output from the 1'1' terminal. As a result, there is no refresh operation of the dynamic memory part (5), and this is completed. Then, the completion point t5 ((teRE
The TI' end signal (FIG. 2(g)) is output to REF-FF- and the refresh signal generating section (2), and each is reset.

Thereafter, similar operations are repeated.

Since the conventional dynamic memory access circuit is configured as described above, even if a read/write operation request is issued from the CPU section, the contention control section (3)
In the worst case, the user has to wait for one clock period (Ta period in the case of FIG. 2), which has the disadvantage of causing a decrease in the operating speed of the CPU.

Also, in the refresh operation, there is a drawback that, in the worst case, the refresh operation is forced to wait for one clock period (Tb period in the case of 2), as in the read/write operation.

This invention was made in order to eliminate all the drawbacks of the conventional ones as described above. When a read/write operation request is generated from the CF3I section, the refretune request is executed in real time without any waiting time. By controlling the competition with 1tl1 work, the CPU operation speed can be increased to 6 speeds.
The purpose of this invention is to provide an access circuit for a dynamic memory that can be used in a dynamic memory.

Below, I will explain an actual case of this invention.

In the third (S I, the signs ill , (2+ , +
5+ is the same as that in FIG. 1 of slave 1 (6) receives the R/W operation request signal from the CPU section (1) and the RBF operation request signal from the reflux signal generation tL section (11) in real time. Competition system (goods) competition Ntll (goods) department (
In the so-called meshichiri “ruri + 7 part)” Konoha! joint sub-part (6
) are the R/Ws connected via the inverters 16D, +62&, to which the R/W and FtEF operation request signals are input, respectively, and the inverters (6i), t62).
and REF reception case (631, f64 7,
(7) Reception gate 1631° (hearing output is 1', -
, 11II Select FF manually input to R11 terminal, +
651 and “OII 11” of this select FFf851.
R/W fed by gate 1lilJ by 111 terminal output
and REF output gate! 66+, Akatsuki, 1j Yohiko's both gates), (Gated by @, 1 signal RA and Ru operation request signal (61) ~ Sleep's 11J path operation time,
11) (Going over 7y)
It is made up of.

In addition, the R/W reception gate 163) and the RP21" reception gate 1 + 641 &
Actually F! It has a -87 rip 7og function, and it also has a -+, select FF function.
Since the terminal is grounded, it is also essentially an R-8 flip-flop.

Next, the operation fc in FIG. 3 and the time chart in FIG. 41 will be explained.

As in the past, the operating conditions for the memory part (5) are based on read/write operation requests from the CPU section full K and refresh requests from the refresh signal generation section (2). There are two, each occurring asynchronously.

Now, if a redundant R/W operation request IJ from the CPU unit (1) occurs at time t1 (at this time, the
(:・yaj Assuming that no request for ij has occurred), that・
Kosui Tei +4-(・64Figure 0・)) is a real-time competition! bll Kanzuki, pano Jε descends to R/~V reception game 1- +631 via I7 heart (61) of 1 ni (()), Through +l141, 10V 1・Ji′F((δ)’s ′′Tze′′・terminal is manually inputted to °°L゛° level (fυ4 ward b
)).

At this time, 11 (+I+ terminal is "H" l/bell, I> (a, +Ql (a)). As a result, Sereno h]'F:1i51 is reset,
, rt/w exit gate (open)
(Reet/Shi [operation request signal 7J) is input to the dynamic memory (5). In this state, at time t2, the REF operation request signal (sound 41
'yl fh)) is generated, this request signal Rli
;F9-included game!・Select FFt through (64)
11 level to “H”
'° level. However, in this case I+7;
Since the H terminal is read/write/101 operation request/C, all "H" level is maintained, so select F +651 becomes 1 inch with all reset states before t2 maintained, and refresh is performed. Operation requests are made to wait.

Dynamic memory part (5) is R/W output game 1-
+66) is the lead output from the gate.
After receiving the rJJ work request number, execute the first assistant work and complete -J-, then the 'jIE J' styling t3 and R
/W generates the end signal (FIG. 4(g)) and resets the CPU name [1's read/write operation I location] kru.

Next, at time 3, when this read/write operation request is set, the REF operation request signal (REF reception game day 641, R/v reception gate ta3) which has been waiting since time ℃2 is sent to tlQ ``C''. Cell, 'cut FF; 6.
51 K is input, and the "S" terminal is set to the "L" level. As a result, select ■ (65) is set, and the R
The FP/output gate (G force becomes active, and the RKF start signal (
FIG. 4 (1)) is generated.

This RBF start signal executes a refresh operation of the dynamic memory part (5), and when it is completed (at time t4), the RFP end signal (Fig. 4 (,i)
) is output to the k refresh signal generator (2), and its l
'F Reset operation request number 1-. Thereafter, the same operation is repeated, and competing collateral of F/W and REF proboscising requests is performed.

As stated above, by this invention (4, The Theory) IJJ
Read/Write and Refret using RS Fliff 70 horn which does not require a clock in 1i11J work/1.・7 volumes of Hf real tights, so it will be executed with this, CPU0 student 61r will also last yj'J
) There is an effect that can be obtained from the business luck of the i-lower suheed.

[Brief explanation of the drawing]

Figure 1 shows the subordinate dynamic menu [Access N]
(g 1y, l, Fig. 2 i, j: m 1 Fig.'
7) Made by IJJ! r K・,l Qll −j−:l
-> Timing 1000 yard diagram, Figure 3 is -t of this invention
7414 is a timing chart 1 to explain the operation of FIG. 3. (1)...CPU section, (2)...Refresh signal generation f:, JS, (3)...Competitive system G1 former capital, (4)...
Tarokku generation 1jls, (5 tarokku memory section,
(6j・-・Competitive system 1st part.The same sign in 1-1 is the same-t 7j i-1:if ”+ r<1< minute. Agent Kuzu !I!Jllgi −

Claims (1)

[Claims] In an access circuit that controls conflict between a read/write operation request and a refresh operation request to a dynamic memory, first and second R-S flips 70 are connected in cascade, and the first R-87IJ7'7o7" (7
) The above read/write operation request (No. 4. 1. An access circuit for a dynamic memory, characterized in that an operation request signal is outputted from a gate, and each gate output is used as the dynamic memory write/write signal and refresh signal.