JPH02172096A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To relieve the load of a control circuit by providing a control circuit controlling a switch circuit through the use of any output from plural systems of address generating circuits and the result of operation of the set value of a data hold circuit. CONSTITUTION:In the write block, an output WX of a 1st address circuit 1 and an output WY of a 2nd address circuit 2 generate a different address pattern synchronously with a reference clock CK. Thus, the address pattern WX, WY are generated in mixture in the address signal WA. The switching of the circuit 5 is controlled by an output WC of the circuit 4. The output WC is generated by inputting the output WX and the output WR being the setting value of a data hold circuit 3 to the circuit 4 as the result of calculation of the outputs WX, WR by the circuit 4. Thus, the load of the control circuit required at the outside of the semiconductor storage device is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device incorporating an address generation circuit.

2. Description of the Related Art In recent years, the field of application of semiconductor memory devices has expanded and they have come to be used in various fields. A large number of dedicated semiconductor memory devices have appeared for each field. For example, there are semiconductor memory devices that have an address generation circuit built into them.

A semiconductor memory device incorporating a conventional address generation circuit will be described below. FIG. 5 is a block diagram of a semiconductor memory device incorporating a conventional address generation circuit, in which 1 is a write address generation circuit, 2 is a read address generation circuit, 3 is a control circuit for controlling write or read operations of the memory, 5 is a memory block, and 4 is a switch circuit for selecting an address signal to be input to the memo block.

The operation of the conventional semiconductor memory device configured as described above will be described below.

The write address generation circuit 1 and the read address generation circuit 2 are mainly constructed using counters. When a write reset signal is input to the write address generation circuit and an initial address value of the write address generation circuit is inputted from the write initial address input terminal, the address value sequentially incremented from the initial address value in synchronization with the reference clock is generated. The address signal WA having the address signal WA is output. Similar to the above operation, the read address generation circuit also outputs RA in synchronization with CK. - A control signal R/W is generated by the control circuit 3 and inputted to the switch circuit 4 to determine whether to perform a memory write operation or a read operation. The control signal R/W
The switch of the switch circuit 4 is connected to WA or RA, and the address signal connected to the switch becomes the address signal MA transferred to the memory block 5, so that the memory cell corresponding to the address value of the address signal MA is selected from among the memory blocks.

Problems to be Solved by the Invention However, the conventional configuration described above has only one address generation circuit on each of the writing side and reading side, and the address signals WA and RA are incremented in sequence in synchronization with the reference clock CK. It is impossible to mix a random address generation pattern in an address generation pattern that only increments the address value in a semiconductor memory device with a built-in conventional address generation circuit, and A control circuit was required outside the semiconductor memory device containing the address generation circuit. Even when a general-purpose random access memory is used, it is necessary to generate an input address signal externally, and an address generation circuit and a control circuit are required outside the random access memory. As described above, when configuring a system that requires both an increment pattern and a random address generation pattern, using a conventional semiconductor memory device would place an extremely large burden on the external control circuit, resulting in a large system. There was a problem with this.

The present invention solves the problem that the conventional system becomes large, and the present invention is a semiconductor memory device that can significantly reduce the burden of a control circuit required outside the semiconductor memory device and easily realize system simplification. The purpose is to provide equipment.

Means for Solving the Problems To achieve this object, a semiconductor memory device of the present invention includes a plurality of systems of address generation circuits, a switch circuit and a data holding circuit for switching between the plurality of systems of address generation circuits, and A control circuit is provided for controlling the switch circuit using an output of one of the plurality of address generation circuits and a calculation result of a setting value of the data holding circuit.

Effect: With this configuration, the load on the control circuit required outside the semiconductor memory device can be significantly reduced, and the system can be easily simplified. Furthermore, the switching operation of multiple systems of address generation circuits can be automatically controlled within the present semiconductor memory device, and the degree of freedom in memory address generation patterns can be improved.

EXAMPLES Below, a semiconductor memory device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In the write block shown in FIG. 1, 1 is a first address generation circuit, and 2 is a second address generation circuit, each of which generates different systems of address values WX and WY. 3 is a data holding circuit which outputs an output signal WR. 5 is a switch circuit for switching between WX and WY; 4 is a switch circuit for switching between WX and WR;
This is a control signal that outputs the control signal WC to the control signal WC. For read blocks, the same configuration as for write operations is developed. 1
1 is a control circuit that controls the operation of the memory block; 12 is a control circuit that controls the operation of the memory block;
13 is a switch circuit that switches according to the output R/W of the control circuit, and 13 is a memory block that writes or reads data.

The operation of the semiconductor memory device of this embodiment configured as described above will be described below with reference to the block diagram of FIG. 1 and the timing diagram of FIG. 2.

First, as shown in FIG. 1, the write block has two systems of address generation circuits, a first address generation circuit 1 and a second address generation circuit, in the same operation block, and as shown in FIG. The output WX of address generation circuit 1 and the second
The output WY of the address generation circuit is automatically generated within the semiconductor memory device using different address generation patterns in synchronization with the reference clock CK. Therefore, by switching the switch of the switch circuit 5 from WX to WY or from WY to WX, the address signal WA in the write block can be generated by mixing the WX and WY address generation patterns, and the address signal WA can be generated by mixing the WX and WY address generation patterns. A degree of freedom can be given to the generation pattern. In other words, as shown in Fig. 2, by switching the switch of the switch circuit 5 from the WX, which generates an increment pattern, to the WY, which has a different address generation pattern, the address value can be skipped to an arbitrary value, or the same address value can be changed. You can perform actions such as repeating.

The switch operation of the switch circuit 5 described above is controlled by the output WC of the control circuit 4. The WC transmits to the control circuit 4 the output WX of the address generation circuit, which is generated while incrementing the address value, and a plurality of data indicating which arbitrary value of the WX signal should be used to switch the switch circuit 5. It is generated as a result of inputting two signals, the output WR of the data holding circuit, to the control circuit 4, and calculating the WX and the WR by the control circuit 4. The control circuit 4 has a circuit that detects whether the values of the WX and WR signals match or not, and as shown in FIG. 2, in the initial state, WC is at "L" level,
A switch of the switch circuit 5 is connected to the first address generation circuit 1, and WX is used as a write address signal WA. Next, when the control circuit 4 detects that the values of WX and WR match, WC changes from the "L" level to the "H" level,
A switch of the switch circuit 5 is connected to the second address generation circuit 2, and WY is set as the WA.

The state in which the switch of the switch circuit 5 is connected to the second address generation circuit is maintained until the control circuit 4 detects that WX matches WR again and the switch of the switch circuit 5 is switched. Here, the operation of the control circuit 4 is controlled in a third manner.
This will be explained with reference to the figures and FIG. FIG. 3 shows the circuit configuration of the control circuit 4 and data holding circuit 3 in FIG. 1, 103 and 104 are gate circuits, and
The gate circuit 103 outputs the exclusive OR of the output WX of the address generation circuit 100 and the output 5TAT of the second register, and the gate circuit outputs the exclusive OR of the output END of the first address generation circuit 100 and the second register. This is the circuit 104. Gate circuit 103.1
Input signals WX and 5TAT and WX and EN by 04
A match detection circuit is configured to detect whether or not D matches. 106 is a composite gate circuit that combines an OR gate and an AND gate, and the output EX of the composite gate is D.
Input to flip-flop. The D flip-flop synchronizes with the reference clock CK, takes in the EX at the rising edge of the CK, and outputs OUT. The output signal OUT corresponds to the control signal WC in FIG. The OR gate of the composite gate circuit receives the output EQ+ of the gate circuit 103 and the output O of the D flip-flop.
Enter UT. The 'A N D gate has a configuration in which the output of the OR gate and the output EQ2, which is obtained by inverting the polarity of the output of the gate circuit 104 via an inverter circuit 105, are input. The operations of the control circuit 4 and data holding circuit 3 shown in FIG. 1 having the above configuration will be explained with reference to FIG. 4. First, as an initial setting, the address value a7 for switching the switch of the switch circuit 5 in FIG.
Set a17 to END in T. Also, when the reset signal RESET is input to the first address generation circuit 1, the value of the address signal WX becomes al+a2...a n + a
nil is generated while being sequentially incremented in synchronization with the reference clock CK. Next, gate circuit 10
3, when it is detected that the WX and the 5TAT match at a7, the output EQ+ of the gate circuit 103 becomes "H" level by one clock width of the reference clock CK. At this time, WX and END do not match, and the output of the gate circuit 104 passes through the inverter circuit 105, so that EQ2 becomes "H" level. Since the EQ+ input to the OR gate in the composite gate is at "H" level, the output of the OR gate is "H" regardless of the state of the input OUT to the other OR gate.
” level and is input to the AN gate in the composite gate 106.The input EQ2 to the other AND gate is H.
" level, so the output EX of the composite gate becomes "H" level. Next, the D flip-flop outputs the composite gate 10.
The output EX of 6 is latched at the rising edge of the reference clock CK, and the input normal rotation signal OUT is output in synchronization with the reference clock CK. This signal OUT becomes "H" level and is fed back as an input to the OR gate in the composite gate. Next, since WX becomes a8, the output EQ+ of the gate signal 103 becomes "L" level, but the OR circuit in composite gate 106 outputs "H" level. On the other hand, EQ2 is still at "H" level, and the outputs EX and D of the composite gate
The output OUT of the flip-flop is in the “H” level state a (
a7 to a18) are held, and the switching operation of the switch circuit 5 in FIG. 1 is not performed. The above state is maintained until the gate circuit 104 detects that the address values of the outputs END and WX of the second register 102 match. That is, when the output of the OR circuit is at "H" level and the END and WX match at a17, EQ2 becomes "L" level by one clock width of the reference clock CK.

Therefore, the output EX of the composite gate circuit becomes "L" level, this state is latched by the D flip-flop 107, and OUT becomes "L" level. When OUT becomes “L” level, the output of the OR gate in the composite gate becomes M L
, TI level, and EX can maintain the "L level" state until EQ+ becomes "H" level, regardless of the state of EQ2.As described above, the switching operation of the switch circuit 5 is as follows. By incorporating the first address generation circuit 1, data holding circuit 3, and control circuit 4 as in this semiconductor memory device, the switch operation for switching and using a plurality of address generation circuits can be performed independently within the semiconductor memory device. It becomes possible to control.

Note that the address values of the first address generation circuit 1 and the second address generation circuit 2 can be set to initial values by inputting a reset signal.

Furthermore, the setting data can be rewritten in the first register 101 and the second register 102.

The read block operates in the same manner as the write block described above, and generates a read address signal RA. Further, the operation of inputting an address signal to the memory block is similar to the operation of the previous embodiment, and the control circuit 11 controls the operation of writing or reading from the memory block 13.
The switch of the switch circuit 12 is connected to either WA or RA by the output R/W signal. The signal on the side to which the switch 12 is connected is input to the memory block 13 as a memory address signal MA. Memory data can be written to or read from memory cells in the memory block 13 selected by the MA multiplication signal.

As described above, according to this embodiment, by switching between the first address generation circuit 1 and the second address generation circuit 2 using the switch circuit 5, an address is automatically generated within the present semiconductor memory device, and moreover, the address is automatically generated within the semiconductor memory device. Allows flexibility in addresses. Further, the output of the data holding circuit 3 and the output of the first address generation circuit 1 are input to a control circuit 5, and the operation of the switch circuit 5 is determined by the control circuit depending on whether or not both outputs match. Switch operations can be automatically controlled within the present semiconductor memory device. In other words, the load on the circuit can be significantly reduced by using an external device to control the present semiconductor memory device.

Effects of the Invention The present invention provides a plurality of address generation circuits in a semiconductor memory device, a switch circuit for switching the plurality of address generation circuits, a data holding circuit, and an output of one of the plurality of address generation circuits and the data. By having a control circuit for controlling the switch circuit using the calculation result of the set value of the holding circuit, it is possible to automatically generate an address signal within the semiconductor memory device, and it is possible to give the address signal a degree of freedom. can. Furthermore, the switch operation for switching between the plurality of systems of address generation circuits can be automatically controlled. Therefore, the load on the circuit can be significantly reduced by using an external device for controlling the present semiconductor memory device, so that the system can be made small (and easily realized).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing diagram of FIG. 1, and FIG. 3 is an internal circuit configuration of the control circuit and data holding circuit shown in FIG. 1. 4 is a timing diagram of FIG. 3,
FIG. 5 is a block diagram of a semiconductor memory device incorporating a conventional address generation circuit. Name of agent: Patent attorney Shigetaka Awano and one other person
Figure diagram

Claims (2)

[Claims] (1) A plurality of address generation circuits, a switch circuit for switching between the plurality of address generation circuits, a data holding circuit, and a calculation result of the output of any one of the plurality of address generation circuits and the set value of the data holding circuit. 1. A semiconductor memory device comprising: a control circuit for controlling said switch circuit. (2) The data holding circuit has a first register and a second register, and the control circuit includes a gate circuit that detects coincidence between the first register and the output of any one of the plurality of address generation circuits. , a gate circuit that detects coincidence between the outputs of the second register and the address generation circuit, a composite gate circuit that inputs the outputs of both the gate circuits and the output of the main control circuit, and a reference to the output of the composite gate circuit. 2. The semiconductor memory device according to claim 1, further comprising a D flip-flop that latches in synchronization with a clock.