JPS5940528A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a short channel MOSFET by a method wherein deep connection layers are formed in the positions selfaligning with opening parts without changing depths of source.drain layers. CONSTITUTION:The source and the drain 15a, 15b of depths of 0.2mum degree are formed by ion implantation and annealing on a P type Si substrate according to the usual method. The openings 17a, 17b are formed, P ions are implanted 18a, 18b by more high energy, the more high dose quantity, and laser is applied. The layers 18a, 18b are molten by absorbing energy, epitaxial growth is executed continuously, and the connection layers 19a, 19b containing P are generated. Depths thereof depend upon intensity of the laser light, and the layers are formed by selfalignment with the windows 17a, 17b. Because the parts of the layers 15a, 15b not implanted with P ions are covered with an insulating film 16, and moreover annealng is finished and crystallinity is restored, absorption of the laser light is a little to generate to heat, and depths are not changed. Although displacement reaction layers 21a, 21b are generated at the contact parts of metal wirings 20a, 20b and the layers 19a, 19b, because they are covered by the layers 19a, 19b, leakage is not generated, and the highly reliable short channel IGFET can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and relates to ion implantation and subsequent activation.

Conventionally, in insulated gate type (hereinafter MOS type) field effect semiconductor devices with a short channel length and high IJt before integration, the effective channel length of the gate! In order to make the opposing distance between the source and drain regions under the shelf as long as possible, the source and drain regions should have junctions as shallow as possible to minimize the intrusion of the source and drain regions into the housing below the gate electrode. It is used. When a metal layer for wiring is brought into direct contact with the source and drain regions having shallow junctions in this ridge, a substitution reaction between a part of the source and drain regions and the metal layer occurs at the connection g, and the metal layer is connected to the source and drain regions. A leakage current occurs because it penetrates the drain region. Conventional methods for preventing this leakage Figure 1 (a)
, shown in (b).

A thick field oxide film 2 and gate oxide layer 3 are grown on the surface of the semiconductor substrate 1 using a known selective oxidation technique, a gate electrode 4 made of polycrystalline silicon is formed, and using this gate electrode 4 as a mask, for example, silicon arsenic ions are implanted. Source and drain regions 5a, 5b'ji=? J. Next, a vapor phase growth film 6 is formed, and openings 7a+7b for connection are formed (FIG. 1(a)).

Subsequently, through the openings 7a and 7bk, for example, phosphorus is diffused into the semiconductor substrate 1 through heat treatment to form the connection regions 8a and 7b.
8bk is formed, and then connected to the connection region 8a t 8b via the opening ff1s7a17b to form the interconnection region 9aa9b (FIG. 1(b)).

In this conventional example, the source and drain regions 5a + 5b
Arsenic, which has a small diffusion coefficient, is used as an impurity in the connection region 8a.
, 8b, if phosphorus with a large diffusion coefficient is used as an impurity, for example, the connection region 8
By forming the connection regions sa and 8b with a depth of about 1.0 μm, it is possible to obtain the source and drain regions 5a and 5b with a depth of about 0.4 μm at the same time. .

8b has a relatively deep junction and an opening 7a.

Since it is positioned in a self-aligned manner with 7b, it spreads around the opening, so even after the metal wiring regions 9a, 9b are formed, the metal wiring regions 9a, 9b penetrate into the semiconductor substrate 1 due to a substitution reaction. Area 10a.

10bl"l: No leakage occurs because the connection areas 8a and 8b are completely covered. However, in the conventional example described in FIGS. 1(a) and 1(b), the connection areas 10a and 10b are formed by heat treatment. Therefore, even if arsenic with a small diffusion coefficient is selected as the impurity for the source and drain regions 5a and 5b, redistribution of the impurity distribution still occurs, and the source and drain regions 5a and 5b
51) was deepened, and the gate was therefore greatly recessed in the source and drain regions 5a and t5b below the pole 4, the effective channel length was shortened, and the withstand voltage of the device was lowered.

For example, the depth of the hot part in 6σ (in the case of !lt, the source/drain region 5 a + 51) increases from about 0.2 μm to about 0.4 μm.

The present invention eliminates the above-mentioned drawbacks, and without changing the depth of the source and drain regions, has a deep contact F at a position self-aligned with the opening. , it is possible to form a region.

That is, the present invention provides an MO8 type field effect semiconductor device having north and drain regions with a shallow junction metal 41 and a short channel length. The object of the present invention is to obtain a +trt structure in which the generation of current is suppressed without substantially changing the impurity distribution in the source and drain regions.

The inventive feature resides in a method of manufacturing a semiconductor device in which ions are implanted into a semiconductor substrate and the implanted portion is then irradiated with original energy. For example, adjacent to the whole surface of the semiconductor substrate,
Ge I/insulating film and the above Ge)! a source and drain region adjacent to a side surface of the pole, extending within the semiconductor substrate and spaced apart from each other; In manufacturing an MO3 field effect semiconductor device 1g having a deep junction and a connection region extending within the semiconductor substrate, an opening penetrating the insulating film covering the source and drain regions is formed. After forming, ions of an impurity having the same type as the source and drain regions are implanted into the mJ semiconductor substrate through the opening, and then by irradiation with source energy such as a laser beam or a xenon lamp source,
By activating the impurity, the impurity distribution in the source/drain region is substantially changed without using a high temperature process. , a step of forming a wiring layer head electrically connected to the connection region; : A method of manufacturing a semiconductor device including:

Next, the entire structure of the present invention will be explained according to the embodiment shown in FIGS. 2(a) to 2(c).

A thick field oxide film 12 and a gate thickening film 13' are formed on the surface of the semiconductor substrate 11 by a known selective oxidation technique, and then a pole 14 is formed on the polycrystalline silicon gate.
Then, arsenic is ion-implanted and annealed to form the source 1 and drain regions 15a415bk.
Form. The depth of the source and drain regions varies depending on the ion implantation temperature and implantation energy, but ions of 5 x 1 d"/cm2 were implanted at an energy of 1501 ceV and 1 at 900°C. When annealing is performed for a certain period of time, a bond with a depth of about 0.2 μm can be obtained.Subsequently, a vapor phase insulating film 16 is grown, and an opening 17a for connection is formed.

17b is formed. Phosphorous ions are then implanted through the openings 17a and 17b to form an implanted region 18a.

Form 18bk. The ion implantation conditions for phosphorus are, for example, energy 200 k e V,
(This is done at Tn2 (Fig. 2(a)).

Next, as shown in FIG. 2(b), the semiconductor substrate 1 is irradiated with a laser beam to implant ions 110 and 18a.

By absorbing 18bVc light energy to generate heat, melting the implanted regions 18a and 18b and continuously epitaxially growing them, a connecting region 19a containing phosphorus is formed.
, 19b. The depth of the connection areas 19a and 19b depends on the strength of the laser source, but is, for example, 1.5X10J.
/m2 connection area 19a of about i,0 μm by irradiation with an intensity of
191) It can be obtained in a self-aligned manner with respect to the fully open hole portions 17a and 17blC.

Source and drain regions 1 without phosphorus ion implantation
5a and 15b are stored in the insulating film 16, and the accumulation of impurities has already been annealed in the previous process and the crystallinity has been restored, so the original absorption is small and no heat is generated. It is hardly affected by laser irradiation, and the depth is maintained at approximately 0.2 μm. As for the laser irradiation in this step, the same effect can be expected even if the laser irradiation is performed using a xenon lamp or the like that provides the same source energy.

Subsequently, the metal wiring layers 20a, 20b are connected to the connection regions 19a, 19b through the openings, and the metal wiring layers 205L, 20 are connected to the source and drain regions 15a, 15b.
Figure 2 (c) where electrical continuity can be established with b.
.

Metal wiring layers 20a, 20b and connection region 19a.

At the contact portion with 19b, regions 21a and 21b where the metal wiring layers 19a and 19b penetrate into the semiconductor substrate 1 are formed by the above-mentioned substitution reaction, but as shown in FIG. 19a and 19b, so no leakage current occurs.0 As described above, according to the present invention, the metal wiring area and the source,
Since it is possible to form a connection region deeper than the source/drain region at the contact portion of the drain region in a self-aligned manner with respect to the opening without changing the impurity distribution of the source/drain region, it is possible to reduce the MO8 type electric field. The present invention realizes high reliability and high integration of semiconductor devices.

[Brief explanation of the drawing]

Figures 1 (a) and (b) t-j are cross-sectional views showing the conventional manufacturing method at step Jllf4, and Figures 2 (a) to (c) each show the manufacturing method of the uninvented embodiment at step JIN. FIG. In the figure, 1...semiconductor substrate, 2...
...Field oxide film, 3...Gate mization 71
%, /I...Gate 11L pole, 5a15b...
...J region above source/drain 1j, 6...Insulating film, 7a, 7b...--Opening portion, 8a, 8b...
・・・・Connection area, 9a19b ・・・・Metal interconnection
M region, 10a, 10b...metal infiltration region, 1
DESCRIPTION OF SYMBOLS 1... Semiconductor base, 12... Field oxide film, 13... Gate oxide film, 14...
... Gate electrode, 15a, 15b ... Lease, drain region, 16 ... Insulating film, 17 a
e 17 b ・” ・”h hole, 18 a, 18
b --Ion implantation region, 19a, 19b-...
. . . Connection region, 20 a , 20 b . . . metal wiring region, 21 a ) 21 b . . . metal infiltration region. Z 7 figure (0)

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising ion-implanting impurities into a semiconductor substrate, and then irradiating the implanted portion with light energy. −