JPS5936874A - Processor of vector - Google Patents

Abstract

PURPOSE:To execute saving at the generation of an interruption or resetting at the time of release efficiently, by setting up a vector effective display flag to execute a vector instruction when the flag is on and to generate an interruption at the off of the flag. CONSTITUTION:A scalar instruction or a vector instruction is set up in an instruction register 10. The instruction is decoded by a scalar decoding part 11 or a vector decoding part 12. The scalar instruction is sent from the scalar decoding part 11 to a scalar operating part 8 and the vector instruction is sent from the vector decoding part 12 to a vector operating part 9 through a gate 14. An AND gate 14 is opened when the vector effective display flag 13 is set up. An AND gate 15 is opened when the flag 13 is reset. If the vector instruction is decoded when the AND gate 15 is opened, an interruption controlling part 16 generates and interruption.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a vector valid flag (flip-flop).
The present invention relates to a vector processing device which generates an interrupt when a vector instruction is attempted to be executed when a vector valid flag is off.

[Conventional technology and problems]

FIG. 1 is a diagram showing an overview of a computer system including a vector processing device, and FIG. 2 is a diagram showing an overview of the vector processing device. In FIG. 1, 1 is a main memory unit, 2 is a memory control unit, 3 and 4 are channel processing units, 5 is a central processing unit, and 6-digit vector processing unit, respectively. The memory control unit 2 includes each processing device 3.4.5.6.
It controls access to the main storage unit 1 of the main memory unit 1. The number of buses between the vector processing device 6 and the memory control unit 2 is larger than the number of buses between the other processing devices 3, 4.5 and the memory control unit 2, for example, four buses are provided. This allows data to be transferred at high speed. A plurality of buses are also provided between the main memory unit and the memory control unit 2.

FIG. 2 shows an outline of the vector processing device.

In FIG. 2, 7 is an instruction control section, 8 is a scalar operation section,
9Fi vector calculation units are shown. The vector processing device includes an instruction control section 7, a scalar operation section 8, and a vector operation section 9, and further includes general-purpose registers, vector registers, etc., although not shown. The six vector processing units are equipped with a large number of vector registers in order to process vector data quickly and efficiently, and a plurality of data buses are connected to the above-mentioned memory control unit 2. The provided vector processing device executes scalar instructions executed by the scalar operation section and vector instructions executed by the vector operation section. The vector instruction is the vector instruction above.
They can be roughly divided into data transfer instructions between registers and main memory unit 1, and arithmetic instructions that process data on vector registers. By the way, when executing a program, input/output interrupts, program interrupts, Interrupts such as supervisor call interrupts occur, and corresponding program processing is required.

When an interrupt occurs, at least the registers necessary for system maintenance must be saved to the main memory unit 1. Unfortunately, when resuming execution of a program that has been interrupted, the saved information must be restored to its original state. It takes a lot of work to set it up again. By the way, in a vector processing device, in order to perform vector operation η, it is necessary to save and reset necessary registers belonging to the vector processing function, including the vector register. However, because
For example, a vector register has 513 x 256 (elements) x 16 (pieces) of digits, so even if it is transferred at high speed using multiple data buses provided between it and the main memory unit 1, it will take a considerable amount of time. Thank you for taking your time. Performing such processing goes against the purpose of the n[ period, which is to perform high-speed processing on the vector processing device.

[Purpose of the invention]

The present invention is based on the above considerations, and in a vector processing device that is capable of performing scalar arithmetic processing and vector arithmetic processing, when the save processing or interrupt processing that is performed when an interrupt occurs is completed, The purpose of the present invention is to provide a vector processing unit that can efficiently perform resetting processing and the like.

[Structure of the invention]

Therefore, the vector processing device of the present invention is a vector processing device having a scalar operation section that executes scalar instructions and a vector operation section that executes vector instructions. The above vector effective display flip
When the flop is on, the vector operation part can execute a vector instruction, and when the vector valid display flip-flop is off and an attempt is made to execute a vector instruction, an interrupt is generated. [Embodiments of the Invention] The present invention will be described below with reference to the drawings.

3. I'l+ is a block diagram of one embodiment of the main part of the instruction control section according to the present invention, and FIG. 4 is a diagram illustrating the operation when an interrupt occurs.

In FIG. 3, numeral 10 indicates an instruction register, an 11-digit scalar instruction decoding section, 12 a vector instruction decoding section, a 13-digit vector valid display flip-flop, 14 and 15 digit ANI) gates, and a 16-digit interrupt control section. ing. The instruction register 10 is set with a scalar instruction or a vector instruction. UP coat of commands (operation)
Code) C. The scalar instruction w1 reader] 1 or is decoded by the vector instruction decoder 12. When the instruction is a scalar instruction, instruction control information is sent from the scalar instruction decoding section 11 to the scalar performance section 8, and when the instruction is a vector instruction, instruction control information is sent from the vector instruction decoding section 12 to the gate 14.
The signal is sent to the vector calculation unit 9 via. ANI) gate 14 opens when the vector valid indication flip-flop is set.

Also, the A,ND gate 15 is open when the vector valid display flip-flop is being reset. A
When a vector instruction is decoded while the ND gate 15 is open, the interrupt control unit 1G generates an interrupt. The vector valid display clip flop 13 is
It is also possible to set (set/reset) by a command and make this command a privileged command.

FIG. 4 is a diagram 1' showing the operation when an interrupt occurs. The interrupt function is system, internal, external, and precepts are determined by the company's own requirements. This is a function that changes the state of the 11th inn. The 10 types of interrupts include input/output interrupts, external interrupts, program interrupts, supervisor call interrupts, machine check interrupts, and restart interrupts. The execution program is switched by these interrupts.

The transition between the blocks in FIG. 4 involves an interrupt processing program. In Figure 4, Norokuram 1
This is a program that uses vector instructions, and programs 2 and 3 are ugly programs that use vector instructions. Whether or not to use a vector instruction, specify it for each block in advance.
Tube 13 is shown.

By executing the interrupt processing program, the program that was running at a straight speed and ? Maintaining and setting the state of the program to be executed at 'K' 1. R or something like that was done 2. In the example shown in Fig. 4, from the point at which program 1 is interrupted to the point at which it is restarted, vector registers and other vector registers (11! Registers included in the function (hereinafter referred to as vector registers) ) of ilj R, f iJ- have not been performed.In such a case, it is necessary to save these vector registers.

In the present invention, when an interrupt occurs, the relationship between the previously executed program and the next executed program is determined by KI.
This provides a means of preserving Ni1 when determining whether it is necessary to save all AI vectors and registers.

For this purpose, the interrupt processing program according to the present invention,
- Newly perform processing such as FNα.

■ Next, the execution operation progera 11 uses vector instructions.1. When the vector valid display flip-flop 13 is turned off.

■ When the next program to be executed uses vector instructions, the vector valid display flip-flop 13
is set to on, and checks whether the most recently executed program among the programs using vector instructions is the same as the next program to be executed.

■ If it is determined that the situation is different from before,
Maintains and sets vector registers.

Vector instructions are not used in processing such as input/output interrupts. That is, it is considered that in many cases, a vector instruction is not used until an interrupt occurs, the corresponding program processing is performed, and the original program is returned. In that case, there is no need to maintain or set vector registers using interrupts.

As mentioned above, in the present invention, the principle is to instruct each blockrum in advance whether or not to use vector instructions. However, if a vector instruction is executed in the middle, the interrupt control unit 16 will generate an interrupt even if the vector instruction is executed due to an instruction error or programming error in the process that was supposed to be executed. , it is possible to completely save and set registers. Furthermore, vector effective display flip 70 tube 1
3 can be set by an instruction, but by making that instruction a privilege instruction, that is, by making it possible to set it only by the interrupt processing program, this function becomes more practical and effective. [Effect of the invention] As is clear from the above description, according to the present invention, the vector processing device i! performs scalar arithmetic processing and vector arithmetic processing 011. In , it is possible to efficiently save and set registers at the time of interrupt generation and at the time of control removal, and it is possible to dramatically improve the processing efficiency of the vector processing device. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of a computer system including a vector processing device, FIG. 2 is a diagram showing an overview of a vector processing device,
FIG. 3 is a block diagram of one embodiment of the main part of the instruction control section according to the present invention, and FIG. 4 is a diagram showing the operation when an interrupt occurs. DESCRIPTION OF SYMBOLS 1... Main memory unit, 2... Memory control unit, 3 and 4... Channel processing device, 5... Central processing unit, 6... Vector processing device, 7... Instruction control unit,
8... Scalar operation unit, 9... Vector operation unit, 10
...Instruction register, 11...Scalar instruction decoder, 1
2...Vector instruction 1'lf reading section, ]3...Vector valid display flip flow rough, 14 and 15...AN
L) Gate, 16... Interrupt control unit. Patent Applicant Fujitsu Limited Representative Patent Attorney Kyotani 4th Department Procedural Amendment (Voluntary) May 27, 1980 Commissioner of the Patent Office Kazuo Wakasugi (Examiner of the Japan Patent Office) 1. Indication of the case 1981 Patent Application No. 146916
No. 2, Name of the invention Vector processing device 3, Draw 1]: Relationship with the case of the person who does
Address 5 Name (522) Representative of Fujitsu Ltd. 111 copies each ``) (Shin 4, Contents of agent amendment 1. The scope of claims in the specification is amended as follows. ``α) Scalar instruction In a vector processing device having a scalar operation section for execution, a vector operation section for executing vector instructions, and a vector valid display flip-flop which can be set by a program, - when the hector valid display flip-flop is on, the vector operation section and means for generating an interrupt when an attempt is made to execute a vector instruction when the vector valid display flip-flop is off. Device. (21 vector effective display flip-flop 71r I
f? The vector processing device according to claim 1, wherein the vector processing device can be set only by an lli instruction. 2, Specification Wff, page 5, line 12, page 6, line 1, ``The scalar instruction...is a feature.'' is corrected as follows. A vector processing unit that has a scalar operation part that executes scalar instructions, a vector operation part that executes vector instructions, and a vector valid display flip-flop that can be set with one program, and when the vector valid display flip-flop is on. Features include a means for enabling the vector operation section to execute a vector instruction, and a means for generating an interrupt when a vector instruction is attempted to be executed when the vector valid display flip-flop is off. 3. On page 7, line 9 of the specification, add the following sentence after "...is possible." That is, when the OP code is decoded and the instruction is to set the vector valid display flip-flop 132 cents, the vector valid display flip-flop 13 is set, and when the command is to reset the vector valid display flip-flop 132 cents, the vector valid display flip-flop 13 is set. The display flip-flop 13 is reset.''4. Correct as shown in FIG. 3 and the accompanying drawings. Age 3 and above

Claims (1)

[Scope of Claims] In a vector processing device having a scalar operation section that executes scalar instructions and a vector operation section that executes vector instructions, a vector effective display flip-flop that can be set by a program is provided, and the vector effective display flip-flop・When the flop is on, the vector operation part can execute a vector instruction, and if a vector instruction is attempted to be executed when the vector valid display flip-flop is off, an interrupt is generated. vector processing device. (2) The vector processing device according to claim (1), wherein the vector valid display flip-flop can be set only by a privileged instruction.