JPH07110772A - Data processor - Google Patents

Abstract

PURPOSE:To provide a data processor capable of preserving an internal state in an interruption processing or the like without lowering an operating speed or destructing data. CONSTITUTION:The value of the number of registers to be used as general purpose registers in a register group 21 is set in the register field 24 of a PSW beforehand and the remaining registers are defined as the registers to be used for a stack area. A pointer to which the value is set as an initial value is provided and it is increased/decreased by a computing element 26. PUSH and POP are performed to the registers to be used for the stack area with the value of the pointer 25 as a register number and the system of the preservation processing of the internal state is selected by an interruption level or the kind of a specific instruction accompanying the utilization of the stack area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device using a microprocessor or the like, and more particularly to saving an internal state at the time of interruption and recovering the internal state at the time of resumption by its interrupt processing.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view showing an interrupt processing by a conventional data processing apparatus. In the figure, 1 is a main routine and 2 is an interrupt processing routine executed by an interrupt request. Interrupt processing routine 2
In the figure, 3 is a register value saving processing unit that saves the internal register value to an external memory, 4 is a main body processing unit that is the main body of the interrupt processing routine 2, and 5 is a register value that restores the saved internal register value. It is a recovery processing unit.

Next, the operation will be described. In a data processing device that reads instructions from the outside and sequentially executes the instructions, when an interrupt request of another process having a high priority occurs while a certain instruction sequence (for example, main routine 1) is being executed,
The data processing device transfers the processing from the instruction sequence being executed at that time to another instruction sequence (interrupt processing routine 2) to be executed at the time of the interrupt request. When the processing of this other instruction sequence is completed, the process returns to the original instruction sequence and continues the process from the point where it was interrupted. In this way, in order to temporarily suspend the processing of the instruction sequence that is being executed, execute another instruction sequence that has nothing to do with it, and restart the processing of the instruction sequence that was interrupted after the processing was completed, The internal state such as the register value at the time must be saved, and the internal state must be restored when restarting.

In a data processing device such as an 8-bit microprocessor, the internal register value is saved and restored by a PUSH (push) instruction and a POP (pop) instruction.
This is done using instructions called instructions. That is,
As shown in FIG. 4, when an interrupt request occurs during execution of the main routine 1, the process proceeds to the interrupt processing routine 2. In the interrupt processing routine 2, the register value saving processing unit 3 uses the PUSH instruction to save the data in the internal register to the external memory. After that, the processing of the main body processing unit 4 of the interrupt processing routine 2 is executed.
When the processing of the main body processing unit 4 ends, the register value recovery processing unit 5 uses the POP instruction to return the previously saved data from the external memory to the original internal register. In this way, after the data in the internal register is restored, the processing of the main routine 1 is restarted.

However, in such a system, when an interrupt occurs, it is necessary to access the external memory twice as many times as the number of internal registers to be saved, so that the processing speed is inevitably reduced. Therefore, there is also proposed a data processing device which is provided with an auxiliary register group therein and is provided with an instruction for switching between the normal register group and the auxiliary register group.

FIG. 5 is a block diagram showing a data processing device by a microprocessor provided with such an auxiliary register group. In the figure, 11 is a general-purpose register group as a normal register group including a plurality of general-purpose registers, and 12 is a general-purpose register group as an auxiliary register group including a plurality of general-purpose registers. 13 is a switching circuit for switching the write / read signals of the general-purpose register groups 11 and 12, 14 is a control unit for generating the switching signal of the switching circuit 13, and 15 is data to which the general-purpose register groups 11 and 12 are connected. It's a bus.

Next, the operation will be described. The switching circuit 13 switches the output destination of the read / write signal between the general-purpose register group 11 and the general-purpose register group 12 each time the switching signal is received from the control unit 14. Here, the switching circuit 13 is set so that a read / write signal is output to the general-purpose register group 11 when the microprocessor is started up. The control unit 14 outputs a switching signal to the switching circuit 13 when an exchange command (hereinafter referred to as an EX command) for exchanging the general-purpose register groups 11 and 12 is executed.

Therefore, if the EX instruction is executed at the start of the interrupt processing routine, the general-purpose register group used until then, for example, the general-purpose register group 11 cannot be read or written, and the internal register can be accessed without accessing the external memory. The data of can be saved. Further, if the EX instruction is executed again at the end of the interrupt processing routine, the stop of the read / write of the general-purpose register group 11 is released, and the data of the internal register can be restored without accessing the external memory.

However, when the EX instruction is executed in the main processing unit of the interrupt processing routine, that is, the EX instruction is executed before the internal register value is restored at the end of the interrupt processing routine. In this case, since the general-purpose register group 11 stopped at the start of the interrupt processing routine can be read and written at that time, there is a possibility that the data of the internal register that should have been saved will be destroyed. .

[0010]

Since the conventional data processing apparatus is configured as described above, if it becomes necessary to hold the internal state in interrupt processing or the like, the processing speed is lowered due to access to the external memory. In addition, if hardware such as an auxiliary register is added to prevent a decrease in operating speed, the internal state may not be completely retained in some cases. There was a problem.

The present invention has been made in order to solve the above-mentioned problems, and retains the internal state required for interrupt processing and the like without lowering the operation speed and destroying data. It is an object of the present invention to obtain a data processing device that can be performed so as not to occur.

[0012]

According to a first aspect of the present invention, there is provided a data processing device in which a value is written to specify how many registers in a register group including a plurality of registers are used as general-purpose registers. A status register that stores a status word with fields, the value written in this register field is set as an initial value, and the value is incremented and decremented by the arithmetic unit and used as a stack area in the register group. Of the specified register used as a general-purpose register and a pointer that specifies one of the pointers, and the stored data in the register specified by the pointer is used as a general-purpose register. Equipped with transfer means to transfer to the specified register used It is intended.

The data processing device according to the second aspect of the present invention includes a transfer means according to the result of comparison between the value written in the interrupt level field of the status word and the interrupt level input from the outside. It is provided with a comparator for controlling whether or not it is valid.

Further, in the data processor according to the present invention as defined in claim 3, when one of the specific instructions is decoded by the instruction decoder, the stack use instruction field in the status word is referred to and based on the value thereof. The transfer means is provided with a function of controlling whether or not data transfer processing between data stored in a predetermined register used as a general-purpose register and a register designated by a pointer is performed.

[0015]

In the pointer according to the first aspect of the invention, the value written in the register field of the status word stored in the status register is set as an initial value, and the value is incremented and decremented by the operation unit to register the register. One of the registers used as a stack area in the group is designated, and the transfer means transfers the data stored in a predetermined register used as a general-purpose register to the register designated by this pointer, and by this pointer By transferring the data stored in the specified register to the specified register used as a general-purpose register, the register specified by the pointer is used as the stack area to ensure the internal state without degrading the operating speed. A data processing device that can be stored in

Further, the comparator in the invention described in claim 2 compares the interrupt level input from the outside with the value written in the interrupt level field of the status word, and activates the transfer means according to the comparison result. By doing so, it is determined whether or not the register designated by the pointer is used as the stack area.

The transfer means in the invention described in claim 3 is based on the value of the stack use instruction field in the status word when one of the specific instructions is decoded,
By enabling its own transfer process, it is determined whether the register designated by the pointer is used as a stack area.

[0018]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1. In the figure, 21 is a plurality, for example, 1
It is a register group including six registers R1 to R16, and 22 is a data bus to which the register group 21 is connected. Reference numeral 23 is a status register for storing a processor status word (hereinafter referred to as PSW) which is a status word showing an internal status, and 24 is the register group 21.
Is a register field in the PSW in which a value for designating how many of the registers R1 to R16 are used as general-purpose registers and the remaining ones to be used as a specific register serving as a stack area is written. .

Reference numeral 25 is a pointer to which the value written in this register field 24 is set as an initial value, and which indicates one of the registers used as a stack area, and 26 is the value of this pointer 25. It is an arithmetic unit that increments and decrements. Reference numeral 27 denotes a control unit that performs overall control of the microprocessor as the data processing device, and identifies data stored in a predetermined register used as a general-purpose register in the register group 21 as a stack area. Transfer to a register specified by the value of the pointer 25 in the register, and transfer the data stored in the specific register specified by the value of the pointer 25 to a predetermined register used as a general-purpose register It has a function as a means.

Reference numeral 28 is a stack pointer in which a value for designating an external memory to which the data stored in the register to be PUSHed is transferred when a memory connected to the outside is used as a stack area. Reference numeral 29 is a comparison register for holding a value to be compared with the value stored in the stack pointer 28, and reference numeral 30 is for comparing the value of the stack pointer 28 with the value of the comparison register 29 to obtain the comparison result. It is a comparator that outputs to the control unit 27. An instruction decoder 31 decodes an instruction read from the outside.

Next, the operation will be described. Here, when the register group 21 is formed by 16 registers R1 to R16 as described above, the PSW has a 4-bit register field 24, and the pointer 25 has a 4-bit data portion and a 1-bit flag. It has a 5-bit structure consisting of parts. The user first sets 1 of the register group 21.
It is determined how many of the six registers R1 to R16 will be general-purpose registers and the rest will be specific registers to be used as a stack area. For example, if it is decided to use 10 registers as general-purpose registers and the remaining 6 registers as specific registers, PSW register field 2
In “4”, “1010” is written. It should be noted that this writing is performed by an instruction for writing to the PSW.

When the instruction decoder 31 decodes the instruction, it writes the value "1010" contained in the instruction code to the register field 24 of the PSW stored in the status register 23 and also inputs it to the pointer 25. To do. By performing such initial settings, the number of general-purpose registers that can be used by the user on the program becomes 10 registers R1 to R10.

When the PUSH instruction is executed in such a state, the control unit 27 causes a register in the register group 21 whose register number is a value obtained by incrementing the value of the pointer 25 by 1 by the calculator 26, that is, in this case. Writes the data of the general-purpose register to be PUSH into the register R11. The value of the pointer 25 after writing to the register R11 is “1011” because it is incremented by 1 by the computing unit 26. When the POP instruction is executed next, this pointer 2
The data having the value "1011" of 5 as the register number, that is, the data of the register R11 is written to the general-purpose register for POP. After this writing is completed, pointer 2
The value of 5 is decremented by 1 by the calculator 26 and returned to "1010".

When the PUSH instruction is successively generated and the value of the pointer 25 is incremented to exceed "1111", "1" is set in the flag portion of the pointer 25 to cause an overflow. Display that. When the flag of the pointer 25 is on, the control unit 27 writes the data of the general-purpose register to be PUSHed into the external memory designated by the value of the stack pointer 28. At the same time, "0000" is written to the pointer 25, and the value of the stack pointer 28 at this time is written to the comparison register 29. After that, the PUSH instruction is executed using the value of this stack pointer 28.

On the other hand, when the POP instruction is executed after the value is written in the comparison register 29, the POP data is read from the external memory designated by the stack pointer 28, and the value of the stack pointer 28 is compared with the data. The value in the register 29 is compared with the comparator 30.
As a result of the comparison, if the two match, the control unit 27 causes the pointer 2
The flag of 5 is cleared to "0". When the POP instruction is executed when the flag is not set, the control unit 27 performs the POP using the pointer 25 described above. However, the value of the pointer 25 immediately after the flag is cleared is "0000". In such a case, the data read from the register R16 in the register group 21 is set to P
Write to a general-purpose register to be OPed. After the writing is completed, the value of the pointer 25 is decremented by the calculator 26 to become "1111".

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the invention described in claim 2. In the figure, 21 is a register group, 22 is a data bus, 23 is a status register, 2
4 is a register field, 25 is a pointer, 26 is a computing unit, 27 is a control unit having a function as a transfer unit, 28
Is a stack pointer, which is the same as or equivalent to the one denoted by the same reference numeral in FIG.

Further, 32 is set at a position different from the register field 24 of the PSW stored in the state register 23, and designates the interrupt level at which the internal state saving process based on the value of the pointer 25 in the first embodiment is performed. This is the interrupt level field to which the value to be written is written. Reference numeral 33 is a comparator which compares the interrupt level input from the outside with the value of the interrupt level field 32 and controls the validity / invalidity of the function of the transfer means of the control unit 27 according to the comparison result.

Next, the operation will be described. The user sets a value in the register field 24 of the PSW stored in the status register 23 as in the case of the first embodiment, and
A value is also set in the interrupt level field 32.
The value set in this interrupt level field 32 is
At the time of saving the data stored in the register in the interrupt processing, PUSH and POP using the pointer 25 are performed, or normal PUSH using the stack pointer 28 is performed.
And used to select whether to perform POP.

When an interrupt is requested from the outside, the control unit 27 compares the interrupt level with the value set in the interrupt level field 32 by the comparator 33. As a result of the comparison, if the interrupt level of the interrupt requested from the outside is lower than the value set in the interrupt level field 32, the PUSH and POP in the interrupt processing are the pointers 25 described in the first embodiment. And the register group 21 are used inside the data processing device. On the other hand, if the requested interrupt level is higher than the set value of the interrupt level field 32, the stack pointer 28 is used to execute PUSH and POP with the memory externally connected to the data processing device.

Thus, according to the second embodiment,
By using the pointer 25, PUSH and POP performed inside the data processing apparatus can be executed only for the interrupt request of the priority desired by the user.

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the invention described in claim 3. Corresponding parts are designated by the same reference numerals as those in FIG. 1 and their explanations are omitted. In the figure, 34 is set at a position different from the register field 24 of the PSW stored in the status register 23, and is based on the value of the pointer 25 described in the first embodiment for each specific instruction involving the use of the stack area. This is a stack use instruction field in which a value designating whether or not to save the internal state is written.

Incidentally, the control unit 27 which realizes the transfer means.
Is the PS stored in the status register 23 when any of the specific instructions is decoded by the instruction decoder 31.
This is different from that of the first embodiment in that the stack use instruction field 34 of W is referred to and whether or not the function of the transfer means is validated is determined based on the value.

Next, the operation will be described. The instruction to write data to the stack area includes the PUSH instruction and PO.
In addition to the P instruction, there are a plurality of types of instructions such as a branch instruction to a subroutine. Therefore, in the third embodiment,
A 1-bit field is provided as a stack use instruction field 34 for each specific instruction that involves the use of the stack area, and "0" is used when an external memory is used as the stack area, and when the internal register group 21 is used. Writes "1" there.

When one of the specific instructions involving the use of the stack area is decoded by the instruction decoder 31, a stack use signal and a signal unique to each specific instruction are sent to the control unit 27. The control unit 27 controls the P stored in the status register 23.
The corresponding field of the stack use instruction field 34 of SW is searched, and if the value set therein is "0", the stack pointer 28 is used to stack the memory connected to the outside of the data processing device. P as region
Perform USH or POP. On the other hand, if the value set therein is "1", PUSH or POP is performed using the pointer 25 using the register group 21 inside the data processing device as a stack area. The operation using the pointer 25 is the same as that in the first embodiment.

[0035]

As described above, according to the first aspect of the present invention, the pointer in which the value of the register field of the PSW is set as the initial value is provided, and the value is incremented and decremented by the arithmetic unit, Since one of the registers used for the stack area in the register group is designated, access to the external memory does not occur and the operation speed is reduced when saving / restoring the internal state. Not only that, but the area of the register used by a normal program and the area of the register for saving the internal state are strictly distinguished from each other to prevent the destruction of data and enable the reliable saving of the internal state. , Furthermore, it becomes possible for the user to set the area freely,
This has the effect of making more effective use of hardware.

According to the second aspect of the invention, the interrupt level and the PS input from the outside by the comparator are
Since the function of the transfer means is compared with the value of the interrupt level field of W and the function of the transfer means is made effective according to the comparison result, the PUSH using the pointer and the internal register group is used.
Since the POP and the POP can be performed only for the interrupt request of the priority desired by the user, the limited hardware can surely suppress the decrease in the operation speed of the processing desired by the user. is there.

According to the invention of claim 3, P
Based on the value of the stack use instruction field in SW,
Since it is configured to select the method of saving the internal state in each specific instruction involving the use of the stack area, PUSH and POP using the pointer and the internal register group are selected.
Can be performed only for a specific instruction desired by the user, and the limited hardware has an effect that the operation speed of the processing desired by the user can be surely suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a data processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a data processing device according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a state of interrupt processing by a conventional data processing device.

FIG. 5 is a block diagram showing a data processing device including a conventional auxiliary register group.

[Explanation of symbols]

 21 register group 23 status register 24 register field 25 pointer 26 arithmetic unit 27 control unit (transfer means) 31 instruction decoder 32 interrupt level field 33 comparator 34 stack use instruction field

Claims (3)

[Claims] 1. A register group consisting of a plurality of registers for storing data, and a value designating how many of the registers in the register group are used as general-purpose registers and the remaining number is used as a specific register. A status register in which a status word having a register field to be written is stored; a pointer to which the value written in the register field is set as an initial value; an arithmetic unit for incrementing and decrementing the value of the pointer; The data stored in a predetermined one of the registers used as the general-purpose registers is transferred to the one designated by the value of the pointer in the register used as the specific register, and is used as the specific register. Stored in the value specified by the pointer in the register And a transfer means for transferring the stored data to a predetermined one of the registers used as the general-purpose registers. 2. The status word stored in the status register has an interrupt level field in which a value designating an interrupt level for carrying out a transfer process based on the value of the pointer is written, and an interrupt level input from the outside is stored. The data processing apparatus according to claim 1, further comprising a comparator that compares the value of the interrupt level field and validates the transfer means according to a comparison result. 3. A stack use in which a status word stored in the status register has a value designating whether or not to perform a transfer process based on the value of the pointer, which is written for each specific instruction accompanied by use of a stack area. An instruction field is provided, and the transfer means refers to the stack use instruction field when any of the specific instructions is decoded by the instruction decoder, and determines whether to perform the transfer process based on the value. The data processing device according to claim 1, wherein the data processing device is a device.