JPS5720864A - Vector processor - Google Patents

Vector processor

Info

Publication number
JPS5720864A
JPS5720864A JP9394880A JP9394880A JPS5720864A JP S5720864 A JPS5720864 A JP S5720864A JP 9394880 A JP9394880 A JP 9394880A JP 9394880 A JP9394880 A JP 9394880A JP S5720864 A JPS5720864 A JP S5720864A
Authority
JP
Japan
Prior art keywords
vector
instruction
register
shunt
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9394880A
Other languages
Japanese (ja)
Inventor
Takashi Kawabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9394880A priority Critical patent/JPS5720864A/en
Publication of JPS5720864A publication Critical patent/JPS5720864A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To reduce the time required for the shunt and recovery of a vector transistor and thus increase the efficiency of a vector processor, by inhibiting a part of an interruption followed by a shunt of the vector register in a vector processor. CONSTITUTION:An instruction (SDO instruction) is supplied to an instruction register 5 to start a vector operation that extracts the vector elements successively out of the vector registers to perform an operation. Thus an instruction decoder 6 decodes the SDO instruction and sets an instruction holding state flip-flop 7. As a result, the interruptions such as input/output interruption, etc., if produced, are inhibited since an AND circuit 8 is closed. When a vector operation and instruction (EDO instruction) is set to the register 5, the flio-flop is reset to cancel the inhibition of interruption. Accordingly no shunt of the vector register is caused by an interruption under a vector operation. Thus the time required for the shunt of the vector register can be eliminated.
JP9394880A 1980-07-11 1980-07-11 Vector processor Pending JPS5720864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9394880A JPS5720864A (en) 1980-07-11 1980-07-11 Vector processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9394880A JPS5720864A (en) 1980-07-11 1980-07-11 Vector processor

Publications (1)

Publication Number Publication Date
JPS5720864A true JPS5720864A (en) 1982-02-03

Family

ID=14096653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9394880A Pending JPS5720864A (en) 1980-07-11 1980-07-11 Vector processor

Country Status (1)

Country Link
JP (1) JPS5720864A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936874A (en) * 1982-08-26 1984-02-29 Fujitsu Ltd Processor of vector
JPS6029870A (en) * 1983-07-28 1985-02-15 Toshiba Corp Vector processing unit
JPS61211745A (en) * 1985-03-15 1986-09-19 Sanyo Electric Co Ltd Microcomputer
JPS61233865A (en) * 1985-04-09 1986-10-18 Nec Corp Vector processor
JPS61235985A (en) * 1985-04-11 1986-10-21 Nec Corp Vector processor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936874A (en) * 1982-08-26 1984-02-29 Fujitsu Ltd Processor of vector
JPS6346872B2 (en) * 1982-08-26 1988-09-19 Fujitsu Ltd
JPS6029870A (en) * 1983-07-28 1985-02-15 Toshiba Corp Vector processing unit
JPH0560141B2 (en) * 1983-07-28 1993-09-01 Tokyo Shibaura Electric Co
JPS61211745A (en) * 1985-03-15 1986-09-19 Sanyo Electric Co Ltd Microcomputer
JPH0452972B2 (en) * 1985-03-15 1992-08-25 Sanyo Electric Co
JPS61233865A (en) * 1985-04-09 1986-10-18 Nec Corp Vector processor
JPS61235985A (en) * 1985-04-11 1986-10-21 Nec Corp Vector processor

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