JPS5935437A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5935437A
JPS5935437A JP57146361A JP14636182A JPS5935437A JP S5935437 A JPS5935437 A JP S5935437A JP 57146361 A JP57146361 A JP 57146361A JP 14636182 A JP14636182 A JP 14636182A JP S5935437 A JPS5935437 A JP S5935437A
Authority
JP
Japan
Prior art keywords
electrode
insulating film
semiconductor device
section
adhesive strength
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57146361A
Other languages
English (en)
Inventor
Yukio Hayakawa
由紀夫 早川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57146361A priority Critical patent/JPS5935437A/ja
Publication of JPS5935437A publication Critical patent/JPS5935437A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、半導体基板と電気的に接続した金属膜（以下
、電極と称す）が、半導体基板上に形成された絶縁膜上
で前記接続面から離れた所に引き出されて、外部端子と
電気的に連結された金属線と接続するところの、引き出
し電極形の半導体装置に関するものである。
従来の引き出し電極形半導体装置の一例の外部端子に連
結する金属線と電極との接続部の平面図およびそのＡ−
Ａ断面図をそれぞれ第１図（ａ）と（ｂ）に示す。これ
らの図において、１は電極で、半導体基板３の上に形成
された絶縁膜２にあけられた窓５を通して半導体基板３
に接続され、絶縁膜２の上に引き出され、金属線４と接
続されている。
上記引出し電極構造でに、電極１と絶縁膜２との、接着
が化学的結合となっていない為に接着強度が弱く、金属
線４に機械的ストレスが加わった場合に、電極１が絶縁
膜２との界面から剥がれて開放故障となることがしばし
ばあった０ 従来、電極１と絶縁膜２との接着強度を強くする方法と
して、金属線４を接続する部分の電極面積を大きくする
方法があった０しかし、！極面積を大きくすると電極と
半導体基板とのＭＯ８容量が太きくなり、半導体装置の
特性に悪影響を及ぼすと云う欠点がある。
本発明は、上記の様なＭＯ８容量が大きくなると云う欠
点を招くことなく、電極と絶縁膜との接着強度が強くさ
れている半導体装置を提供することを目的とする。
つぎに本発明を実施例により説明する。第２図（ａ）、
　（ｂ）ａそれぞれ本発明の一実施例の要部の平面図お
よびそのＡ−Ａ断面図である。これらの図において、電
極１１と金属線１４との接続部の下の絶縁膜１２に複数
個の凹凸１６を設けている。なお、１３に半導体基板、
５は電極と半導体基板の接続部の絶縁膜の窓である。
上記の様に、電極１１と金属線１４との連結部の下部の
絶縁膜に凹凸を設けることにより、！極面Ｓを大きくす
ることなく電極と絶縁膜との接着面積を実質的に大きく
することができる為、　ＭＯ８容量も大きくならずかつ
、１！極と絶縁膜との接着強度も実用上問題ないレベル
を得ることができる。また、絶縁膜の凹凸によジ電極表
面にも凹凸ができる為、電極と金属線との接着面積も広
くなり、その接着強度も向上することができる。
なお、上記実施例において、凹凸の形状に格子縞として
いるが、これはまた、縦または横の単なる縞状でもよい
０
【図面の簡単な説明】
第１図（ａ）Ｕ従来の引き出し電極形半導体装置の外部
端子に連結する金属線と電極との接続部の平面図、同図
（ｂ）ｉ図（ａ）のＡ−Ａ断面図、第２図（ａ）。 （ｂ）はそれぞれ本発明の一実施例の要部平面図および
そのＡ−Ａ断面図である。 １．１１・・・電極、２．１２・・・絶縁膜、３．１３
・・・半導体基板、４．１４・・・金属線、訃・・絶縁
膜の窓、１６・・・絶縁膜の凹凸。 （（１） （レジ 第１　図 （θ〕 とｂノ 第２　図

Claims (2)

    【特許請求の範囲】
  1. （１）半導体基板と、この基板上面に形成された絶縁膜
    と、前記絶縁膜上面に形成され、かつ、前記絶縁膜［ｉ
    けられた窓を通して前記半導体基板と接続されている金
    属膜と、前記絶縁膜の上の金属膜と連結された金属線と
    を備えた半導体装置において、前記金属線と金属膜との
    連結部下部の絶縁Ｍは凹凸面とされていることを特徴と
    する半導体装置。
  2. （２）上記絶縁膜の凹凸面はしま状の凹凸面であること
    を特徴とする特許請求の範囲第１項に記載の半導体装置
    。
JP57146361A 1982-08-24 1982-08-24 半導体装置 Pending JPS5935437A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57146361A JPS5935437A (ja) 1982-08-24 1982-08-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57146361A JPS5935437A (ja) 1982-08-24 1982-08-24 半導体装置

Publications (1)

Publication Number Publication Date
JPS5935437A true JPS5935437A (ja) 1984-02-27

Family

ID=15405975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57146361A Pending JPS5935437A (ja) 1982-08-24 1982-08-24 半導体装置

Country Status (1)

Country Link
JP (1) JPS5935437A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773899A (en) * 1993-09-30 1998-06-30 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Bonding pad for a semiconductor chip
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
USRE40819E1 (en) 1995-12-21 2009-07-07 Micron Technology, Inc. Semiconductor device with improved bond pads
US8027370B2 (en) 2009-02-06 2011-09-27 Sony Corporation Semiconductor device
CN106532432A (zh) * 2015-09-09 2017-03-22 富士施乐株式会社 面发光型半导体激光元件的制造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773899A (en) * 1993-09-30 1998-06-30 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Bonding pad for a semiconductor chip
US5869357A (en) * 1993-09-30 1999-02-09 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Metallization and wire bonding process for manufacturing power semiconductor devices
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
USRE40819E1 (en) 1995-12-21 2009-07-07 Micron Technology, Inc. Semiconductor device with improved bond pads
US8027370B2 (en) 2009-02-06 2011-09-27 Sony Corporation Semiconductor device
CN106532432A (zh) * 2015-09-09 2017-03-22 富士施乐株式会社 面发光型半导体激光元件的制造方法
CN106532432B (zh) * 2015-09-09 2019-07-19 富士施乐株式会社 面发光型半导体激光元件的制造方法

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