JPS5931058A - Variable resistor - Google Patents

Variable resistor

Info

Publication number
JPS5931058A
JPS5931058A JP14140982A JP14140982A JPS5931058A JP S5931058 A JPS5931058 A JP S5931058A JP 14140982 A JP14140982 A JP 14140982A JP 14140982 A JP14140982 A JP 14140982A JP S5931058 A JPS5931058 A JP S5931058A
Authority
JP
Japan
Prior art keywords
transistor
variable resistance
resistance value
resistance element
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14140982A
Other languages
Japanese (ja)
Inventor
Konin Munakata
宗像 恒任
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14140982A priority Critical patent/JPS5931058A/en
Publication of JPS5931058A publication Critical patent/JPS5931058A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802Resistors only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605Resistors with PN junctions

Abstract

PURPOSE:To obtain a variable resistor with small patterns by a method wherein diffusion resistance is formed in a semiconductor of the first conductivity type by means of diffused wiring layers of the second conductivity type, and these wiring layers are designated as the source and drain of a FET for resistance control purpose. CONSTITUTION:The variable resistor is composed of a ladder resistor consisting of diffused resistors 13, 14, and 15, a P-channel FET16, and a P-channel FET18. The FET16 has the source and drain formed by means of the resistors 13 and 14. The FET18 has the source and drain formed by means of the resistors 14 and 15. The resistance value of the variable resistor, i.e., the resistance value between terminals 11 and 12 is made variable by the potentials of gate terminals 18 and 19.

Description

【発明の詳細な説明】 この発明は、半導体集積回路における可変抵抗素子に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable resistance element in a semiconductor integrated circuit.

近年、AD変換回路、DA変換回路を利用した電子機器
が多種多様にわたり数多く開発されており、将来的にも
この傾向が続き、その数も増加することが予想される。
In recent years, a wide variety of electronic devices using AD conversion circuits and DA conversion circuits have been developed in large numbers, and it is expected that this trend will continue and the number of electronic devices will increase in the future.

そして、そのAD変換回路。And that AD conversion circuit.

DA変換回路のほとんどが半導体集積回路圧よって構成
されており、その半導体集積回路化されたAD変換回路
、DA変換回路には可変抵抗素子が必ず使用されている
。すなわち、半導体集積回路における可変抵抗素子は、
特1cAD変換回路、DA変換回路でその需要は増大し
ている。また、その他の回路においても需要が増加する
一方であり、従来の可変抵抗素子についても色々な欠点
を改良してゆくことが要望される。
Most of the DA conversion circuits are constructed of semiconductor integrated circuits, and a variable resistance element is always used in the AD conversion circuits and DA conversion circuits implemented as semiconductor integrated circuits. In other words, the variable resistance element in the semiconductor integrated circuit is
In particular, the demand for 1c AD conversion circuits and DA conversion circuits is increasing. In addition, demand for other circuits continues to increase, and it is desired to improve various drawbacks of conventional variable resistance elements.

従来の半導体集積回路における可変抵抗素子の一例とし
て第1図に示すようなものが一般に用いられている。同
図において、1,2は可変抵抗素子の端子で、この端子
1.2間の抵抗値が変化するのである。3,4.5は拡
散あるいはポリシリコンにより形成されたラダー抵抗体
、6,7はそれぞれ可変抵抗素子の抵抗値を制御するP
チャンネル電界効果トランジスタ(以下単にトランジス
タという)である。トランジスタ6.7がON状態とな
った時のその抵抗値をαとすると、通常αは、ラダー抵
抗体3,4.5の抵抗値1’L、、R2゜R3より極め
て小さい値α< R”+ 、R2、Rsとなるよう設計
されている。8.9は前記トランジスタ6.7のゲート
端子である。
As an example of a variable resistance element in a conventional semiconductor integrated circuit, one shown in FIG. 1 is generally used. In the figure, 1 and 2 are terminals of a variable resistance element, and the resistance value between these terminals 1 and 2 changes. 3, 4.5 are ladder resistors formed of diffusion or polysilicon, and 6, 7 are Ps that control the resistance value of the variable resistance element, respectively.
This is a channel field effect transistor (hereinafter simply referred to as a transistor). If the resistance value of the transistor 6.7 when it is in the ON state is α, then normally α is a value extremely smaller than the resistance values 1'L, , R2°R3 of the ladder resistors 3, 4.5, α<R. 8.9 is the gate terminal of the transistor 6.7.

次に第1図に示す可変抵抗素子の動作について説明する
。まず、第1にトランジスタ6および7のゲート電位が
ともに@H″レベルの時、トランジスタ6および7はと
もにOFFの状態となり、端子1,2間の抵抗値はIt
1+几、+R3となる。第2にトランジスタ6のゲート
電位が″H″レベルでトランジスタ7のゲート電位が”
L″レベル時、トランジスタ6はOFF状態、トランジ
スタIはON状態となり、端子1,2間の抵抗値はR,
十R。
Next, the operation of the variable resistance element shown in FIG. 1 will be explained. First, when the gate potentials of transistors 6 and 7 are both @H'' level, both transistors 6 and 7 are in the OFF state, and the resistance value between terminals 1 and 2 is It
1+几, +R3. Second, when the gate potential of transistor 6 is at "H" level, the gate potential of transistor 7 is "H" level.
At L'' level, transistor 6 is OFF, transistor I is ON, and the resistance value between terminals 1 and 2 is R,
Ten R.

となる。第3にトランジスタ6のゲート電位が”L”レ
ベルの時、トランジスタ6はON状態なので、トランジ
スタTのON、OFFにかかわらず、端子1.2間の抵
抗値はR8となる。このように第1図に示す可変抵抗素
子は抵抗値としてR,+R。
becomes. Thirdly, when the gate potential of the transistor 6 is at the "L" level, the transistor 6 is in the ON state, so the resistance value between the terminals 1 and 2 is R8 regardless of whether the transistor T is ON or OFF. In this way, the variable resistance element shown in FIG. 1 has resistance values of R and +R.

+几、、  R,十R,,R,の3つの抵抗値を供給す
ることができる。もし、供給する抵抗値の数を増やした
い時は、ラダー抵抗体および抵抗値制御用のトランジス
タの数を増やすことにより可能となる。
Three resistance values can be provided: +R, R, and R. If it is desired to increase the number of resistance values to be supplied, this can be done by increasing the number of ladder resistors and resistance value control transistors.

しかしながら、この可変抵抗素子を半導体集積回路とし
てパターン設計する場合は、第2図に示すように各ラダ
ー抵抗体3,4,5および可変抵抗素子の抵抗値制御用
トランジスタ6およびTをそれぞれ別々に設ける必要が
ある。従って、パターンの面積としてかなりの面積を必
要とするため、チップコストが高くなるという欠点があ
った。
However, when designing a pattern for this variable resistance element as a semiconductor integrated circuit, as shown in FIG. It is necessary to provide Therefore, since a considerable area is required for the pattern, there is a drawback that the chip cost increases.

この発明は、上記の点に鑑みてなされたもので、従来の
ものに比べて極めてパターン面積が小さくできる可変抵
抗素子を提供するものである。以下、この発明の一実施
例を図面に基づいて説明する。
The present invention has been made in view of the above-mentioned points, and provides a variable resistance element whose pattern area can be made extremely small compared to conventional ones. Hereinafter, one embodiment of the present invention will be described based on the drawings.

第3図はこの発明に係る可変抵抗素子の一実施例を示す
図である。同図において、11.12は可変抵抗素子の
端子で、アルミニウム等で形成され、この端子11.1
2間の抵抗値が後述のように変化するのである。13,
14.15は拡散抵抗体で形成されたラダー抵抗体であ
る。16は前記ラダー抵抗体13および14をソースお
よびドレインとした可変抵抗素子の抵抗値を制御する分
布状に形成されたPチャンネル電界効果トランジスタテ
する(以下単にトランジスタという)。17は前記トラ
ンジスタ16と同様、ラダー抵抗体14および15をソ
ースおよびドレインとした、可変抵抗値を制御する分布
状に形成されたPチャンネル電界効果トランジスタであ
る(以下単にトランジスタという)。18.19は前記
トランジスタ16.17のゲート端子である。
FIG. 3 is a diagram showing an embodiment of the variable resistance element according to the present invention. In the same figure, 11.12 is a terminal of a variable resistance element, which is made of aluminum or the like, and this terminal 11.1
The resistance value between the two changes as described below. 13,
14 and 15 are ladder resistors formed of diffused resistors. Reference numeral 16 denotes a P-channel field effect transistor (hereinafter simply referred to as a transistor) formed in a distributed pattern for controlling the resistance value of a variable resistance element with the ladder resistors 13 and 14 as sources and drains. Similar to the transistor 16, 17 is a P-channel field effect transistor (hereinafter simply referred to as a transistor) formed in a distributed manner that controls a variable resistance value and uses ladder resistors 14 and 15 as sources and drains. 18.19 is the gate terminal of the transistor 16.17.

次に1上記第3図に示す可変抵抗素子の動作について説
明する。まず第1にトランジスタ16および17のゲー
ト電位がともにH”レベルの時、トランジスタ16およ
び17はともにOFF’の状態となり、可変抵抗素子の
抵抗値、すなわち端子11.12間の抵抗値はR+ +
 J + Raとなる(ただし、R,、IiL、、R,
はそれぞれラダー抵抗体13゜14.15の抵抗値)。
Next, the operation of the variable resistance element shown in FIG. 3 above will be explained. First of all, when the gate potentials of transistors 16 and 17 are both at H'' level, both transistors 16 and 17 are in the OFF' state, and the resistance value of the variable resistance element, that is, the resistance value between terminals 11 and 12 is R+ +
J + Ra (where R,, IiL,, R,
are the resistance values of the ladder resistor 13°14.15, respectively).

第2K)ランジスタ16のゲート電位が″11″レベル
、トランジスタ11のゲート電位がL”レベルの時、ト
ランジスタ16はOFFの状態、トランジスタITはO
Nの状態となり、端子11.12間の抵抗値は R1+
βとなる(ただし、βはラダー抵抗体14と15の直列
合成抵抗と、トランジスタ17がONした状態のそのド
レイン、ソース間の抵抗とを並列接続して得た合成抵抗
値)。第3ICトランジスタ16のゲート電位が”L″
レベルトランジスタ11のゲート電位が”H″レベル時
、トランジスタ16はON状態、トランジスタ17はO
FF状態となり、端子11.12間の抵抗値はR1+γ
となる(ただし、γはラダー抵抗体13と14の直列合
成抵抗と、トランジスタ16のON状態のドレイン。
2nd K) When the gate potential of the transistor 16 is at the "11" level and the gate potential of the transistor 11 is at the L" level, the transistor 16 is in the OFF state and the transistor IT is in the OFF state.
The state is N, and the resistance value between terminals 11 and 12 is R1+
(However, β is the combined resistance value obtained by connecting in parallel the series combined resistance of the ladder resistors 14 and 15 and the resistance between its drain and source when the transistor 17 is turned on.) The gate potential of the third IC transistor 16 is “L”
When the gate potential of the level transistor 11 is at "H" level, the transistor 16 is in the ON state and the transistor 17 is in the OFF state.
It becomes FF state, and the resistance value between terminals 11 and 12 is R1+γ
(However, γ is the series combined resistance of ladder resistors 13 and 14 and the drain of transistor 16 in the ON state.

ソース間の抵抗とを並列接続して得る合成抵抗値)。(combined resistance value obtained by connecting the resistance between sources in parallel).

第4IC)ランジスタ16および17のゲート電位がと
もK”L”レベルの時、トランジスタ16および1Tが
ともKOHの状態になり、端子11.12間の抵抗値は
δとなる(ただし、δはラダー抵抗体13,14.15
とトランジスタ16,17の合成抵抗で、はぼトランジ
スタ16および17がONした状態のドレイン、ソース
間の抵抗を直列接続して得る合成抵抗値)。
4th IC) When the gate potentials of transistors 16 and 17 are both at the K"L" level, both transistors 16 and 1T are in the KOH state, and the resistance value between terminals 11 and 12 is δ (however, δ is the ladder value). Resistor 13, 14.15
and the combined resistance of transistors 16 and 17, which is the combined resistance value obtained by connecting in series the resistances between the drain and source when transistors 16 and 17 are on.

上記のよ5に、第3図に示す可変抵抗素子はその抵抗値
としてRs + Rt + Rs −J+β、R5十γ
As mentioned in 5 above, the resistance value of the variable resistance element shown in FIG. 3 is Rs + Rt + Rs - J + β, R5 + γ.
.

δの4個の抵抗値を供給することができる。いま、α、
β、γ、δ< R1e Rt p Rs となるように
設計すると、可変抵抗素子の供給できる抵抗値はR1十
R2+R,、R,、l丸3.δの4抵抗値となる。
Four resistance values of δ can be provided. Now, α,
When designed so that β, γ, δ< R1e Rt p Rs, the resistance value that can be supplied by the variable resistance element is R1 + R2 + R,, R,, l circle 3. There are four resistance values of δ.

第3図に示す可変抵抗素子を、半導体集積回路のパター
ン図に変換した一例を第4図に示す。同図に示すように
、ラダー抵抗体13,14.15と可変抵抗素子の抵抗
値を制御するトランジスタ16.17のソース、ドレイ
ンか共用できるためパターン面積は、第3図の従来の可
変抵抗素子のパターンに比べて極めて小さく設計できる
FIG. 4 shows an example in which the variable resistance element shown in FIG. 3 is converted into a pattern diagram of a semiconductor integrated circuit. As shown in the figure, since the ladder resistors 13, 14.15 and the source and drain of the transistor 16.17 that controls the resistance value of the variable resistance element can be shared, the pattern area is smaller than that of the conventional variable resistance element shown in Fig. 3. It can be designed to be extremely small compared to the previous pattern.

また、第5図は第3図に示す可変抵抗素子のパターンの
他の実施例を示す図である。同図の鳩舎も第4図のパタ
ーン図と同様、ラダー抵抗体13゜14.15と可変抵
抗体の抵抗値制御用のトランジスタ16,17のソース
、ドレインが共用できるため、パターン面積は第2図に
示す従来の可変抵抗素子のパターンと比べて極めて小さ
く設計できる。
Further, FIG. 5 is a diagram showing another example of the pattern of the variable resistance element shown in FIG. 3. Similarly to the pattern diagram in Fig. 4, the pigeon coop shown in the same figure can share the source and drain of the ladder resistor 13°14.15 and the transistors 16 and 17 for controlling the resistance value of the variable resistor, so the pattern area is the same as that of the second pattern. It can be designed to be extremely small compared to the conventional variable resistance element pattern shown in the figure.

以上詳細に説明したように、この発明に係る可変抵抗素
子は第1導電型半導体領域内圧形成された第2導電型拡
散配線層による拡散抵抗体と、この第2導電型拡散配線
層それ自体をソースやドレ来の半導体集積回路における
可変抵抗素子に比べて極めて小さいパターン面積で可変
抵抗素子ができ、可変抵抗素子を含む半導体チップをよ
り安価に提供できるというすぐれた効果を発揮するもの
である。
As described above in detail, the variable resistance element according to the present invention includes a diffused resistor formed by a second conductivity type diffusion wiring layer formed with an internal pressure of a first conductivity type semiconductor region, and the second conductivity type diffusion wiring layer itself. Compared to variable resistance elements in semiconductor integrated circuits such as sources and drains, a variable resistance element can be formed with an extremely small pattern area, and a semiconductor chip including a variable resistance element can be provided at a lower cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体集積回路における可変抵抗回路図
、第2図はそのパターンに変換した図、第3図はこの発
明に係る半導体集積回路における可変抵抗回路図、第4
図はそのパターンに変換した一例を示す図、第5図は同
じくパターンに変換した他の例を示す図である。 図中、11.12は端子、13,14.15はラダー抵
抗体、16.17はトランジスタである。 なお、図中の同一符号は同一または相当部分を示す。 代理人 葛野信−(外1名) 第1図 第3図 1 手続補正書 (自発) 第4図 617 1 第5図 9 5、補正の対象 11召和5暗「1月26日 1、事件の表示    特願昭57−141409号2
、発明の名称    可変抵抗素子 3、補正をする者 事件との関係   特許出願人 住 所     東京都千代田区丸の内二丁目2番3汗
名 称(601)   三菱電機株式会社代表者片山仁
八部 4、代理人 住 所     東京都千代田区丸の内二丁目2番3号
明細書の発明の詳細な説明の欄および図面6、補正の内
容 (1)  明細書ff14頁3行の[抵抗値制御用トラ
ンジスタ」を、「抵抗値制御用のトランジスタ」と補正
する。 (2)同じく第7頁9行の「第3図」を、「第2図」と
補正する。 (3)図面の第2図、第4図、第5図を別紙のように補
正する。 以に 第4図 第5図 299
FIG. 1 is a diagram of a variable resistance circuit in a conventional semiconductor integrated circuit, FIG. 2 is a diagram converted to a pattern thereof, FIG. 3 is a diagram of a variable resistance circuit in a semiconductor integrated circuit according to the present invention, and FIG.
The figure shows an example of conversion into the pattern, and FIG. 5 is a diagram showing another example of conversion into the same pattern. In the figure, 11.12 is a terminal, 13, 14.15 is a ladder resistor, and 16.17 is a transistor. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Figure 1 Figure 3 1 Procedural amendment (voluntary) Figure 4 617 1 Figure 5 9 5. Subject of amendment 11 Summons 5 Dark "January 26th 1, Incident Display of patent application No. 57-141409 2
, Title of the invention Variable resistance element 3, Relationship to the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitachi Katayama 4; Agent address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Detailed explanation column of the invention in the specification, Drawing 6, Contents of amendment (1) "Resistance value control transistor" on page 14, line 3 of specification ff. , corrected as "transistor for controlling resistance value". (2) Similarly, "Figure 3" on page 7, line 9 is corrected to "Figure 2." (3) Correct the figures 2, 4, and 5 of the drawings as shown in the attached sheet. Figure 4, Figure 5 299

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路における可変抵抗素子において、第1導
電型半導体領域内に形成された第2導電型拡散配線層に
よる複数の拡散抵抗体と、この第2導電型拡散配線層そ
れ自体をソースおよびドレインとして分布状に形成した
抵抗値制御用電界効果トランジスタとからなることを特
徴とする可変抵抗素子。
A variable resistance element in a semiconductor integrated circuit includes a plurality of diffused resistors formed by a second conductivity type diffusion wiring layer formed in a first conductivity type semiconductor region, and the second conductivity type diffusion wiring layer itself serving as a source and a drain. A variable resistance element comprising a resistance value control field effect transistor formed in a distributed pattern.
JP14140982A 1982-08-13 1982-08-13 Variable resistor Pending JPS5931058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14140982A JPS5931058A (en) 1982-08-13 1982-08-13 Variable resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14140982A JPS5931058A (en) 1982-08-13 1982-08-13 Variable resistor

Publications (1)

Publication Number Publication Date
JPS5931058A true JPS5931058A (en) 1984-02-18

Family

ID=15291331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14140982A Pending JPS5931058A (en) 1982-08-13 1982-08-13 Variable resistor

Country Status (1)

Country Link
JP (1) JPS5931058A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267583A (en) * 1992-03-18 1993-10-15 Nec Corp Semiconductor integrated circuit device
JP2013201336A (en) * 2012-03-26 2013-10-03 Citizen Holdings Co Ltd Semiconductor nonvolatile storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267583A (en) * 1992-03-18 1993-10-15 Nec Corp Semiconductor integrated circuit device
JP2013201336A (en) * 2012-03-26 2013-10-03 Citizen Holdings Co Ltd Semiconductor nonvolatile storage device

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